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lpc47n227 100 pin super i/o with lpc interface for notebook applications features ? 3.3 volt operation (5v tolerant) ? pc99 and acpi 1.0b compliant ? programmable wakeup event interface (nio_pme pin) ? smi support (nio_smi pin) ? gpios (29) ? two irq input pins ? xnor chain ? intelligent auto power management ? 2.88mb super i/o floppy disk controller - licensed cmos 765b floppy disk controller - software and register compatible with smsc's proprietary 82077aa compatible core - supports one floppy drive directly - configurable open drain/push-pull output drivers - supports vertical recording format - 16-byte data fifo - 100% ibm compatibility - detects all overrun and underrun conditions - sophisticated power control circuitry (pcc) including multiple powerdown modes for reduced power consumption - dma enable logic - data rate and drive control registers - swap drives a and b - non-burst mode dma option - 48 base i/o address, 15 irq and 3 dma options - forceable write protect and disk change controls ? floppy disk available on parallel port pins (acpi compliant) ? enhanced digital data separator - 2 mbps, 1 mbps, 500 kbps, 300 kbps, 250 kbps data rates - programmable precompensation modes ? serial ports - two full function serial ports - high speed ns16c550 compatible uarts with send/receive 16-byte fifos - supports 230k and 460k baud - programmable baud rate generator - modem control circuitry ? infrared communications controller - irda v1.2 (4mbps), hpsir, askir, consumer ir support - 2 ir ports - 96 base i/o address, 15 irq options and 3 dma options ? multi-mode parallel port with chiprotect - standard mode ibm pc/xt, pc/at, and ps/2 compatible bidirectional parallel port - enhanced parallel port (epp) compatible - epp 1.7 and epp 1.9 (ieee 1284 compliant) - ieee 1284 compliant enhanced capabilities port (ecp) - chiprotect circuitry for protection against damage due to printer power- on - 192 base i/o address, 15 irq and 3 dma options ordering information order numbers: lpc47n227tqfp for 100 pin tqfp package lpc47n227-mn for 100 pin stqfp package LPC47N227-MT for 100 pin tqn package (green, lead-free) lpc47n227-mv for 100 pin stqn package (green, lead-free)
2 ? lpc bus host interface - multiplexed command, address and data bus - 8-bit i/o transfers - 8-bit dma transfers - 16-bit address qualification - serial irq interface compatible with serialized irq support for pci systems - pci nclkrun support - power management event (nio_pme) interface pin ? 100 pin tqfp package and stqfp package ? 100 pin tqn package and stqn package (green, lead-free) general description the smsc lpc47n227 is a 3.3v pc 99 and acpi 1.0b compliant super i/o controller. the lpc47n227 implements the lpc interface, a pin reduced isa interface whic h provides the same or better performance as the isa/x-bus with a substantial savings in pi ns used. the part also includes 29 gpio pins. the lpc47n227 incorporates smsc?s true cmos 765b floppy disk controller, advanced digital data separator, 16-byte data fifo, two 16c550 compatible uarts, one multi-mode parallel port with chiprotect circuitry plus epp and ecp support and one floppy direct drive support. the lpc47n227 does not require any external filter component s, is easy to use and offers lower system cost and reduced board area. the lpc47n227 is software and register compatible with smsc?s proprietary 82077aa core. the true cmos 765b core provides 100% compatibility with ibm pc/xt and pc/at architectures and provides data overflow and underflow protection. the smsc advanced digital data separator incorporates smsc?s patented data separator te chnology allowing for ease of testing and use. the lpc47n227 supports both 1mbps and 2mbps data rates and vertical recording operation at 1mbps data rate. the lpc47n227 also features a full 16-bit internally decoded address bus, a serial irq interface with pci nclkrun support, relocatable configuration ports and three dma channel options. both on-chip uarts are compatible with the ns16c550. one uart includes additional support for a serial infrared interface that complies with irda v1.2 (fast ir), hpsir, and askir formats (used by sharp and other pdas), as well as consumer ir. the parallel port is compatible with ibm pc/at architectures, as well as ieee 1284 epp and ecp. the parallel port chiprotect circuitry prevents damage caused by an attached powered printer when the lpc47n227 is not powered. the lpc47n227 incorpor ates sophisticated power control circuitry (pcc). the pcc supports multiple low power down modes. the lpc47n227 also features software configurable logic (scl) for ease of use. scl allows programmable system c onfiguration of key functions such as the fdc, parallel port, and uarts. the lpc47n227 supports the isa plug-and-play standard (version 1.0a) and provides the recommended functionaity to support windows ?95/?98 and pc99. the i/o address, dma channel and hardware irq of each device in the lpc47n227 may be reprogrammed through the internal configuration r egisters. there are 192 i/o address location options, a serialized irq interface, and three dma channels.
3 table of contents features....................................................................................................................... ....................... 1 general d escription ............................................................................................................ .......... 2 pin config uration.............................................................................................................. .............. 4 description of pin funct ions ................................................................................................... .. 5 buffer type de scripti on........................................................................................................ ...............13 block di agram .................................................................................................................. ...............14 3.3 volt operation / 5 volt tole rance ...................................................................................15 power functionality............................................................................................................ ..................15 vcc power...................................................................................................................... ....................15 vtr s upport .................................................................................................................... ...................15 internal pwrgood ............................................................................................................... .............15 trickle power functiona lity.................................................................................................... ..............15 maximum curr ent va lues ......................................................................................................... ...........16 power management ev ents (pme /sci) .............................................................................................. 16 functional d escription ......................................................................................................... ......17 floppy disk co ntroller ......................................................................................................... .....22 serial port (uart)............................................................................................................. ..............69 infrared in terface ............................................................................................................. ...........86 parallel port .................................................................................................................. ................90 power mana gement ............................................................................................................... ......112 serial irq ..................................................................................................................... ....................116 pci clkrun suppo rt ............................................................................................................. ........120 general p urpose i/o ............................................................................................................ ........123 system management interrupt (s mi) .....................................................................................129 pme su pport.................................................................................................................... ................130 runtime re gisters.............................................................................................................. ..........131 configura tion.................................................................................................................. ..............138 operational descri ption ........................................................................................................ ..173 maximum guar anteed ra tings ..................................................................................................... .....173 dc electrical c haracteri stics .................................................................................................. ...........173 timing di agrams ................................................................................................................ .............177 package outline ................................................................................................................ ...........198
4 pin configuration note: pinouts are the same for the tqfp, tqn, stqfp and stqn packages. lpc47n227 100 pin tqfp drvden0 drvden1 nmtr0 ndskchg nds0 gp24 vss ndir nstep nwdata nwgate nhdsel nindex ntrk0 nwrtprt nrdata nio_pme vtr clocki lad0 lad1 lad2 lad3 nlframe nldrq 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 npci_reset nlpcpd nclkrun pci_clk ser_irq vss gp30 gp31 gp32 gp33 gp34 gp35 gp36 gp37 gp40 gp41 gp42 gp43 gp44 gp45 gp46 gp47 gp10 gp11/sysopt gp12/nio_smi 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 nslctin ninit vcc gp23/fdc_pp irmode/irrx3 irtx2 irrx2 vss gp22 gp21 gp20 gp17 gp16 gp15 vcc gp14/irqin2 gp13/irqin1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 ndtr2 ncts2 nrts2 ndsr2 txd2 rxd2 ndcd2 vcc nri2 ndcd1 nri1 ndtr1 ncts1 nrts1 ndsr1 txd1 rxd1 nstrobe nalf nerror nack busy pe slct vss lpc47n227 100 pin tqfp/tqn
5 description of pin functions tqfp/stqfp tqn/stqn pin # name symbol buffer type per function 1 description lpc interface 23:20 lpc address/ data bus 3-0 lad[3:0] pci_io active high lpc signals used for multiplexed command, address and data bus. 24 lpc frame nlframe pci_i active low signal indicates start of new cycle and termination of broken cycle. 25 lpc dma/bus master request nldrq pci_o active low signal used for encoded dma/bus master request for the lpc interface. 26 pci reset npci_rese t pci_i active low signal used as lpc interface reset. 27 lpc power down (note 2) nlpcpd pci_i active low power down signal indicates that the lpc47n227 should prepare for power to be shut on the lpc interface. 28 pci clock controller nclkrun pci_od this signal is used to indicate the pci clock status and to request that a stopped clock be started. 29 pci clock pci_clk pci_clk pci clock input. 30 serial irq ser_irq pci_io serial irq pin used with the pci_clk pin to transfer lpc47n227 interrupts to the host. 17 power mgt. event (note 7) nio_pme (o12/od12) this active low power management event signal allows the lpc47n227 to request wakeup. floppy disk interface 1 drive density 0 drvden0 (o12/od12) i ndicates the drive and media selected. refer to configuration registers cr03, cr0b, cr1f. 2 drive density 1 drvden1 (o12/od12) i ndicates the drive and media selected. refer to configuration registers cr03, cr0b, cr1f. 3 motor on 0 nmtr0 (o12/od12) thes e active low output selects motor drive 0.
6 tqfp/stqfp tqn/stqn pin # name symbol buffer type per function 1 description 4 disk change ndskchg is this input senses that the drive door is open or that the diskette has possibly been changed since the last drive selection. this input is inverted and read via bit 7 of i/o address 3f7h. the ndskchg bit also depends upon the state of the force disk change bits in the force fdd status change configurati on register (see subsection cr17 in the configuration section). 5 drive select 0 nds0 (o12/od12) ac tive low output selects drive 0. 8 direction control ndir (o12/od12) this high current low active output determines the direction of the head movement. a logic ?1? on this pin means outward motion, while a logic ?0? means inward motion. 9 step pulse nstep (o12/od12) this acti ve low high current driver issues a low pulse for each track-to-track movement of the head. 10 write data nwdata (o12/od12) this ac tive low high current driver provides the encoded data to the disk drive. each falling edge causes a flux transition on the media. 11 write gate nwgate (o12/od12) this active low high current driver allows current to flow through the write head. it becomes active just prior to writing to the diskette. 12 head select nhdsel (o12/od12) this high current output selects the floppy disk side for reading or writing. a logic ?1? on this pin means side 0 will be accessed, while a logic ?0? means side 1 will be accessed. 13 index nindex is this active low schmitt trigger input senses from the disk dr ive that the head is positioned over the begi nning of a track, as marked by an index hole. 14 track 0 ntrk0 is this active low schmitt trigger input senses from the disk dr ive that the head is positioned over the outermost track.
7 tqfp/stqfp tqn/stqn pin # name symbol buffer type per function 1 description 15 write protected nwrtprt is this active low schmitt trigger input senses from the disk drive that a disk is write protected. any write command is ignored. the nwrprt bit also depends upon the state of the force write protect bit in the force fdd status change configuration regist er (see subsection cr17 in the configuration section). 16 read disk data nrdata is raw serial bit stream from the disk drive, low active. each falling edge represents a flux transition of the encoded data. serial ports interface 84 receive data 1 rxd1 is receiver serial data input for port 1. 85 transmit data 1 txd1 o12 transmit serial data output for port 1. 86 data set ready 1 ndsr1 i 97 data set ready 2 ndsr2 i active low data set ready inputs for the serial port. handshake signal which notifies the uart that the modem is ready to establish the communication link. the cpu can monitor the status of ndsr signal by reading bit 5 of modem status register (msr). a ndsr signal state change from low to high after the last msr read will set msr bit 1 to a 1. if bit 3 of interrupt enable register is set, the interrupt is generated when ndsr changes state. note: bit 5 of msr is the complement of ndsr. 87 request to send 1 nrts1 o6 98 request to send 2 nrts2 o6 active low request to send outputs for the serial port. handshake output signal notifies modem that t he uart is ready to transmit data. this signal can be programmed by writing to bit 1 of the modem control register (mcr). the hardware reset will reset the nrts signal to inactive mode (high). nrts is forced inactive during loop mode operation.
8 tqfp/stqfp tqn/stqn pin # name symbol buffer type per function 1 description 88 clear to send 1 ncts1 i 99 clear to send 2 ncts2 i active low clear to send inputs for the serial port. handshake signal which notifies the uart that the modem is ready to receive data. the cpu can monitor the status of ncts signal by reading bit 4 of modem status register (msr). a ncts signal state change from low to high after the last msr read will set msr bit 0 to a 1. if bit 3 of the interrupt enable register is set, the interrupt is generated when ncts changes state. the ncts signal has no effect on the transmitter. note: bit 4 of msr is the complement of ncts.
9 tqfp/stqfp tqn/stqn pin # name symbol buffer type per function 1 description 89 data terminal ready 1 ndtr1 o6 100 data terminal ready 2 ndtr2 o6 active low data terminal ready outputs for the serial port. handshake output signal notifies modem that the uart is ready to establish data communication link. this signal can be programmed by writing to bit 0 of modem control register (mcr). the hardware reset will reset the ndtr signal to inactive mode (high). ndtr is forced inactive during loop mode operation. 90 ring indicator 1 (note 8) nri1 i 92 ring indicator 2 (note 8) nri2 i active low ring indicator i nputs for the serial port. handshake signal which notif ies the uart that the telephone ring signal is detected by the modem. the cpu can monitor the status of nri signal by reading bit 6 of modem status register (msr). a nri signal state change from low to high after the last msr read will set msr bit 2 to a 1. if bit 3 of interrupt enable register is set, the interrupt is generated when nri changes state. note: bit 6 of msr is the complement of nri. 91 data carrier detect 1 ndcd1 i 94 data carrier detect 2 ndcd2 i active low data carrier dete ct inputs for the serial port. handshake signal which notifies the uart that carrier signal is detec ted by the modem. the cpu can monitor the status of ndcd signal by reading bit 7 of modem status register (msr). a ndcd signal state change from low to high after the last msr read will set msr bit 3 to a 1. if bit 3 of interrupt enable register is set, the interrupt is generated when ndcd changes state. note: bit 7 of msr is the complement of ndcd. 95 receive data 2 rxd2 is receiver seri al data input for port 2. ir receive data. 96 transmit data 2 txd2 o12 transmit serial data output for port 2. ir transmit data. infrared interface 61 ir receive irrx2 is ir receive. 62 ir transmit irtx2 o12 ir transmit. 63 ir mode/ ir receive 3 irmode/ irrx3 o6/ is ir mode. ir receive 3. parallel port interface (note 3)
10 tqfp/stqfp tqn/stqn pin # name symbol buffer type per function 1 description 66 initiate output/ fdc direction control (note 4) ninit/ ndir (od14/op14)/ od14 this output is bit 2 of the printer control register. this is used to initiate the printer when low. refer to parallel port de scription for use of this pin in ecp and epp mode. see fdc pin definition. 67 printer select input/ fdc step pulse (note 4) nslctin/ nstep (od14/op14)/ od14 this active low output sele cts the printer. this is the complement of bit 3 of the printer control register. refer to parallel port description for use of this pin in ecp and epp mode. see fdc pin definition. 68 port data 0/ fdc index pd0/ nindex iop14/ is port data 0 see fdc pin definition. 69 port data 1/ fdc track 0 pd1/ ntrk0 iop14/ is port data 1 see fdc pin definition. 70 port data 2/ fdc write protected pd2/ nwrtprt iop14/ is port data 2 see fdc pin definition. 71 port data 3/ fdc read disk data pd3/ nrdata iop14/ is port data 3 see fdc pin definition. 72 port data 4/ fdc disk change pd4/ ndskchg iop14/ is port data 4 see fdc pin definition. 73 port data 5 pd5 iop14 port data 5 74 port data 6/ fdc motor on 0 pd6/ nmtr0 iop14/ od14 port data 6 see fdc pin definition. 75 port data 7 pd7 iop14 port data 7 77 printer selected status/ fdc write gate slct/ nwgate i/ od12 this high active output from the printer indicates that it has power on. bi t 4 of the printer status register reads the slct input. refer to parallel port description for use of this pin in ecp and epp mode. see fdc pin definition.
11 tqfp/stqfp tqn/stqn pin # name symbol buffer type per function 1 description 78 paper end/ fdc write data pe/ nwrdata i/ od12 another status output from the printer, a high indicating that the printer is out of paper. bit 5 of the printer status register reads the pe input. refer to parallel port description for use of this pin in ecp and epp mode. see fdc pin definition. 79 busy/ fdc motor on 1 busy/ nmtr1 i/ od12 this is a status output fr om the printer, a high indicating that the printer is not ready to receive new data. bit 7 of the printer status register is the complement of the busy input. refer to parallel port description for use of this pin in ecp and epp mode. see fdc pin definition. 80 acknowledge/ fdc drive select 1 nack/ nds1 i/ od12 a low active output from the printer indicating that it has received the data and is ready to accept new data. bit 6 of the printer status register reads the nack input. refer to pa rallel port description for use of this pin in ecp and epp mode. see fdc pin definition. 81 error/ fdc head select nerror nhdsel i/ od12 a low on this input from the printer indicates that there is a error condition at the printer. bit 3 of the printer status register r eads the nerr input. refer to parallel port description for use of this pin in ecp and epp mode. see fdc pin definition. 82 autofeed output/ fdc density select 0 (note 4) nalf/ ndrvden0 (od14/op14)/ od14 this output goes low to cause the printer to automatically feed one line after each line is printed. the nalf output is the complement of bit 1 of the printer control register. refer to parallel port description for use of this pin in ecp and epp mode. see fdc pin definition. 83 strobe output/ fdc drive select 0 (note 4) nstrobe/ nds0 (od14/op14)/ od14 an active low pulse on this output is used to strobe the printer data into the printer. the nstrobe output is the complement of bit 0 of the printer control register. refer to parallel port description for use of this pin in ecp and epp mode. see fdc pin definition.
12 tqfp/stqfp tqn/stqn pin # name symbol buffer type per function 1 description general purpose i/o 6, 32-39, 40-47 48, 54-56, 57-59 general purpose i/o (note 9) gp24, gp30-gp37 gp40-gp47 gp10, gp15-gp17, gp20-gp22 (i/o8/od8) dedicated general purpose input/output. 49 general purpose i/o (system option) (note 5) (note 9) gp11/ (sysopt) (i/o8/od8) general purpose input/output. at the trailing edge of hardware reset the gp11 pin is latched to determine t he configuration base address: 0 = index base i/o address 02e hex; 1 = index base i/o address 04e hex. 50 general purpose i/o/ system mgt. interrupt (note 9) gp12/ nio_smi (i/o12/od12)/ (o12/od12) general purpose input/output. active low system manage ment interrupt output. 51 general purpose i/o/ irq input 1 (note 9) gp13/ irqin1 (i/o8/od8)/ i general purpose input/output. external interrupt input. steerable onto one of the 15 serial irqs. 52 general purpose i/o/ irq input 2 (note 9) gp14/ irqin2 (i/o8/od8)/ i general purpose input/output. external interrupt input. steerable onto one of the 15 serial irqs. 64 general purpose i/o/ floppy on parallel port (note 9) gp23/ fdc_pp (i/o8/od8)/ i general purpose input/output. floppy on the parallel port indication. clock pins 19 14mhz clock clocki is 14.318mhz clock input. power pins 53,65,93 vcc (note 6) vcc +3.3 volt supply voltage. 18 vtr (note 6) vtr +3.3 volt standby voltage. 7,31, 60,76 vss vss ground. note: the "n" as the first letter of a symbol indicates an "active low" signal. note 1: buffer types per function on multiplexed pi ns are separated by a slash ?/?. buffer types in parenthesis represent multiple buffe r types for a single pin function. note 2: the nlpcpd pin may be tied high. note 3: the fdd output pins multiplexed in t he parallel port interface are od drivers only and are not affected by the fdd out put driver controls (see subsec tion cr05 in the configuration section).
13 note 4: active (push-pull) output drivers are re quired on these pins in t he enhanced parallel port modes. note 5: the gp11/sysopt pin requires an external pulldown resistor to put the base io address for configuration at 0x02e. an external pullup resistor is required to move the base io address for configuration to 0x04e. note 6: v cc must not be greater than 0.5v above v tr. note 7: this pin is output only and is powered by vtr. note 8: ring indicator pins nri1 and nri2 have input buffers into the wakeup logic that are powered by vtr. these pins are also inputs to vcc powered logic. note 9: gp10-gp17, gp20-gp24 and gp30-gp37 pins have input buffers into the wakeup logic that are powered by vtr. gp40-47 pins are powered by vcc even as inputs. buffer type description i input ttl compatible. is input with schmitt trigger. o6 output, 6ma sink, 3ma source. o8 output, 8ma sink, 4ma source. od8 open drain output, 8ma sink. io8 input/output, 8ma sink, 4ma source. o12 output, 12ma sink, 6ma source. od12 open drain output, 12ma sink. io12 input/output, 12ma sink, 6ma source. od14 open drain output, 14ma sink. op14 output, 14ma sink, 14ma source. iop14 input/output, 14ma sink, 14ma source. backdrive protected. pci_i input. these pins meet the pci 3. 3v ac and dc characteristics. (note 1) pci_o output. these pins meet the pci 3.3v ac and dc characteristics. (note 1) pci_od open drain output. these pins meet the pci 3.3v ac and dc characteristics. (note 1) pci_io input/output. these pins meet the pci 3.3v ac and dc characteristics. (note 1) pci_iclk clock input. these pins meet the pci 3.3v ac and dc characteristics and timing. (note 2) note 1. see the pci local bus specif ication, revision 2. 1, section 4.2.2. note 2. see the pci local bus specificati on, revision 2.1, sect ion 4.2.2. and 4.2.3.
14 block diagram txd1, nrts1, ndtr1 nwdata nrdata ser_irq pci_clk vcc vss nio_pme denotes multifunction pins irtx2, irmode*, txd2, nrts2, ndtr2 irrx2, irrx3*, rxd2, ncts2, ndsr2, ndcd2, nri2 serial irq lpc bus interface v tr clock gen clocki nmtr0, nds0, ndir, nstep, drvden0*, nwgate, hdsel, drvden1*, nwdata smsc proprietary 82077 compatible vertical floppy disk controller core smi pme wdt digital data seperator pre- compensation ntrk0, ndskchg, nindex, nwrtprt, nrdata * 16c550 compatible serial port 1 wdata wclock rclock rdata ncts1, rxd1, ndsr1, ndcd1, nri1 configuration registers general purpose i/o gp10, gp11, gp12*, gp13*, gp14*, gp1[5:7], gp2[0:2], gp23*, gp24, gp3[0:7], gp4[0:7] multi-mode parallel port/fdc mux pd[0:7], busy, slct, pe, nerror, nack nslctin, nalf ninit, nstrobe control, address, data lad0 lad1 lad2 lad3 nlframe nldrq nlpcpd npci_reset acpi block nio_smi* 16c550 compatible serial port 2 with infrared interface nclkrun irqin1*, irqin2*, fdc_pp*
15 3.3 volt operation / 5 volt tolerance the lpc47n227 is a 3.3 volt part. it is intended solely for 3.3v applications. non-lpc bus pins are 5v tolerant; that is, the input voltage is 5.5v max, and the i/o buffer output pads are backdrive protected. the lpc interface pins are 3.3 v only. these signals meet pci dc specifications for 3.3v signaling. these pins are: ? lad[3:0] ? nlframe ? nldrq ? nlpcpd the input voltage for all ot her pins is 5.5v max. these pins include all non-lpc bus pins and the following pins: ? npci_reset ? pci_clk ? ser_irq ? nclkrun ? nio_pme power functionality the lpc47n227 has two power planes: vcc and vtr. vcc power the lpc47n227 is a 3.3 volt part. the vcc supply is 3.3 volts ( nominal). see the operational description section and the maximum current values subsection. vtr support the lpc47n227 requires a trickle supply (v tr ) to provide sleep current for the programmable wake-up events in the pme interface when v cc is removed. the vtr supply is 3.3 volts (nominal). see the operational descr iption section. the maximum vtr current that is required depends on the functions that ar e used in the part. see trickle power functionality subsection and the maximum current values subsection. if the lpc47n227 is not intended to provide wake-up capabilities on standby current, v tr can be connected to v cc . the v tr pin generates a v tr power-on-reset signal to initialize these components. note: if v tr is to be used for programmable wake-up events when v cc is removed, v tr must be at its full minimum potential at least 10 s before v cc begins a power-on cycle. when v tr and v cc are fully powered, the potential difference between the two supplies must not exceed 500mv. internal pwrgood an internal pwrgood logical control is included to minimize the effects of pin-state uncertainty in the host interface as v cc cycles on and off. when the internal pwrgood signal is ?1? (active), v cc > 2.3v (nominal), and the lpc47n227 host interface is active. when the internal pwrgood signal is ?0? (inactive), v cc 2.3v (nominal), and the lpc47n227 host interface is inactive; that is, lpc bus reads and writes will not be decoded. the lpc47n227 device pins nio_pme, nri1, nri2, and most gpios (as input) are part of the pme interface and remain active when the internal pwrgood signal has gone inactive, provided v tr is powered. see trickle power functionality section. trickle power functionality when the lpc47n227 is running under vtr only, the pme wakeup events are active and (if enabled) able to assert the nio_pme pin active low. the following lists the wakeup events: ? uart 1 ring indicator ? uart 2 ring indicator ? gpios for wakeup. see below. the following requirements apply to all i/o pins that are specified to be 5 volt tolerant. ? i/o buffers that are wake-up event compatible are powered by vcc. under vtr power (vcc=0), these pins may only be configured as inputs. these pins have input buffers into the wakeup logic that are powered by vtr.
16 ? i/o buffers that may be configured as either push-pull or open drain under vtr power (vcc=0), are powered by vtr. this means they will, at a minimum, source their specified current from vtr even when vcc is present. this applies to the nio_pme pin only. the gpios that are used for pme wakeup inputs are gp10-gp17, gp20-gp24, gp30-gp37. these gpios function as follows: ? buffers are powered by vcc, but in the absence of vcc they are backdrive protected (they do not impose a load on any external vtr powered circuitry). they are wakeup compatible as inputs under vtr power. these pins have input buffers into the wakeup logic that are powered by vtr. all gpios listed above are for pme wakeup as a gpio function (or alternate function). see the table in the gpio section for more information. the following list summarizes the blocks, registers and pins that are powered by vtr. ? pme interface block ? runtime register block (includes all pme, smi, gp data registers) ? pins for pme wakeup: - gpios (gp10-gp17, gp20-gp24, gp30-gp37) as input - nio_pme as input - nri1, nri2 as input maximum current values see the ?operational descr iption? section for the maximum current values. the maximum vtr current, i tr , is given with all outputs open (not loaded), and all inputs in a fixed state (i.e., 0v or 3.3v). the total maximum current for the part is the unloaded value plus the maximum current sourc ed by the pin that is driven by vtr. the pin that is powered by vtr (as output) is nio_pme. this pin, if configured as a push-pull output, will source a minimum of 6ma at 2.4v when driving. the maximum vcc current, i cc , is given with all outputs open (not loaded), and all inputs in a fixed state (i.e., 0v or 3.3v). power management events (pme/sci) the lpc47n227 offers support for power management events (pmes), also referred to as system control interrupt (sci) events. the terms pme and sci are used synonymously throughout this document to refer to the indication of an event to the chipset via the assertion of the nio_pme output signal on pin 17. see the ?pme suppor t? section. do not connect the nio_pme pin to pci pme pins.
17 functional description super i/o registers the address map, shown below in table 1, shows the addresses of t he different blocks of the super i/o immediately after power up. the base addresses of the fdc, serial and parallel ports, runtime register block and configuration register block can be mov ed via the configuration registers. some addresses are used to access more than one register. host processor interface (lpc) the host processor communicates with the lpc47n227 through a series of read/write registers via the lpc interface. the port addresses for these registers are shown in table 1. register access is accomplished through i/o cycles or dma transfers. all registers are 8 bits wide. table 1 - super i/o block addresses address block name notes base+(0-5) and +(7) floppy disk base+(0-7) serial port com 1 base1+(0-7) base2+(0-7) serial port com 2 ir support fir and cir base+(0-3) base+(0-7) base+(0-3), +(400-402) base+(0-7), +(400-402) parallel port spp epp ecp ecp+epp+spp base + (0-f) runtime registers base + (0-1) configuration note 1: refer to the configuration regist er descriptions for setting the base address.
18 lpc interface the following sub-sections specify the implementation of the lpc bus. lpc interface signal definition the signals required for the lpc bus interface are described in the table below. lpc bus signals use pci 33mhz electrical signal characteristics. signal name type description lad[3:0] i/o lpc address/data bus. multiplexed command, address and data bus. nlframe input frame signal. indicates start of new cycle and termination of broken cycle npci_reset input pci reset. used as lpc interface reset. nldrq output encoded dma/bus master request for the lpc interface. nio_pme od power mgt event signal. allows the lpc47n227 to request wakeup. nlpcpd input powerdown signal. i ndicates that the lpc47n227 should prepare for power to be shut on the lpc interface. ser_irq i/o serial irq. pci_clk input pci clock. nclkrun i/od clock run. allows the lpc47n227 to request the stopped pci_clk be started. lpc cycles the following cycle types are supported by the lpc protocol. cycle type transfer size i/o write 1 byte i/o read 1 byte dma write 1 byte dma read 1 byte the lpc47n227 ignores cycl es that it does not support. field definitions the data transfers are bas ed on specific fields that are used in various combinations, depending on the cycle type. these fields are driven onto the lad[3:0] signal lines to communicate address, control and data information over the lpc bus between the hos t and the lpc47n227. see the low pin count (lpc) interface specification revision 1.0 from intel, section 4.2 for definition of these fields. nlframe usage nlframe is used by the host to indicate the start of cycles and the termination of cycles due to an abort or time-out condition. this signal is to be used by the lpc47n227 to know when to monitor the bus for a cycle. this signal is used as a general notific ation that the lad[3:0] lines contain information relative to the start or stop of a cycle, and that the lpc47n227 monitors the bus to determine whether the cycle is intended for it. the use of nlframe allows the lpc47n227 to enter a lower power state internally. there is no need for the lpc47n227 to monitor the bus when it is inactive, so it can decouple its state machines from the bus, and internally gate its clocks. when the lpc47n227 samples nlframe active, it immediately st ops driving the lad[3:0] signal lines on the next clock and monitor the bus for new cycle information.
19 the nlframe signal functions as described in the low pin count (lpc) interface specification revision 1.0. i/o read and write cycles the lpc47n227 is the target for i/o cycles. i/o cycles are initiated by the host for register or fifo accesses, and will generally have minimal sync times. the minimum number of wait-states between bytes is 1. epp cycles will depend on the speed of the exter nal device, and may have much longer sync times. data transfers are assumed to be exactly 1-byte. if the cpu requested a 16 or 32-bit transfer, the host will break it up into 8-bit transfers. see the low pin count (lpc) interface specification reference, section 5.2, for the sequence of cycles for the i/o read and write cycles. dma read and write cycles dma read cycles involve the transfer of data from the host (main memory) to the lpc47n227. dma write cycles involve the transfer of data from the lpc47n227 to the host (main memory). data will be coming from or going to a fifo and will have minimal sync times. data transfers to/from the lpc47n227 are 1 byte. see the low pin count (lpc) interface specification reference, section 6.4, for the field definitions and the s equence of the dma read and write cycles. dma protocol dma on the lpc bus is handled through the use of the nldrq line fr om the lpc47n227 and special encodings on lad[ 3:0] from the host. the dma mechanism for the lpc bus is described in the low pin count (lpc) specification revision 1.0.
20 power management clockrun protocol see the low pin count (lpc) interface specification reference, section 8.1. lpcpd protocol the lpc47n227 will func tion properly if the nlpcpd signal goes active and then inactive again without npci_reset becoming active. this is a requirement for notebook power management functions. although the lpc bus s pec 1.0 section 8.2 states, "after nlpcpd goes back inactive, the lpc i/f will always be reset using nlrst?, this statement does not apply for mobile systems. nlrst (npci_reset) will not occur if the lpc bus power was not removed. for example, when exiting a "light" sleep state (acpi s1, apm pos), nlrst (npci_reset) will not occur. when exiting a "deeper" sleep state (acpi s3- s5, apm str, std, soft-off), nlrst (npci_reset) will occur. the nlpcpd pin is implemented as a ?local? powergood for the lpc interface in the lpc47n227. it is not used as a global powergood for the chip. it is used to reset the lpc block and hold it in reset. an internal powergood is implemented in lpc47n227 to minimize power dissipation in the entire chip. prior to going to a low-pow er state, the system will assert the nlpcpd signal. it will go active at least 30 microseconds prior to the lclk (pci_clk) signal stopping low and power being shut to the other lpc i/f signals. upon recognizing nlpcpd active, the lpc47n227 will tri-stat e the nldrq signal and do so until nlpcpd goes back active. upon recognizing nlpcpd inactive, the lpc47n227 will drive its nldrq signal high. see the low pin count (lpc) interface specification reference, section 8.2. sync protocol see the low pin count (lpc) interface specification reference, section 4.2.1.8 for a table of valid sync values. typical usage the sync pattern is used to add wait states. for read cycles, the lpc47n227 immediately drives the sync pattern upon recognizing the cycle. the host immediately drives the sync pattern for write cycles. if the lpc47n227 needs to assert wait states, it does so by driving 0101 or 0110 on lad[3:0] until it is ready, at which point it will drive 0000 or 1001. the lpc47n227 will choose to assert 0101 or 0110, but not switch between the two patterns. the data (or wait state sync) will immediately follow the 0000 or 1001 value. the sync value of 0101 is intended to be used for normal wait states, wherein the cycle will complete within a few clocks. the lpc47n227 uses a sync of 0101 for all wait states in a dma transfer. the sync value of 0110 is intended to be used where the number of wait stat es is large. this is provided for epp cycles, where the number of wait states could be quite large (>1 microsecond). however, the lpc47n227 uses a sync of 0110 for all wait states in an i/o transfer. the sync value is driven within 3 clocks.
21 sync timeout the sync value is driven within 3 clocks. if the host observes 3 consecutive clocks without a valid sync pattern, it will abort the cycle. the lpc47n227 does not assume any particular timeout. when the host is driving sync, it may have to insert a very lar ge number of wait states, depending on pci latencies and retries. sync patterns and maximum number of syncs if the sync pattern is 0101, then the host assumes that the maximum number of syncs is 8. if the sync pattern is 0110, then no maximum number of syncs is assumed. the lpc47n227 has protection mechanisms to complete the cycle. this is used for epp data transfers and will utilize the same timeout protection that is in epp. sync error indication the lpc47n227 reports erro rs via the lad[3:0] = 1010 sync encoding. if the host was reading data from the lpc47n227, data will still be transferred in the next two nibbles. this data may be invalid, but it will be transferred by the lpc47n227. if the host was writing data to t he lpc47n227, the data had already been transferred. in the case of multiple byte cycles, such as dma cycles, an error sync terminates the cycle. therefore, if the host is transferring 4 bytes from a device, if the device re turns the error sync in the first byte, the other three bytes will not be transferred. i/o and dma start fields i/o and dma cycles use a start field of 0000. reset policy the following rules govern the reset policy: 1) when npci_reset goes inactive (high), the clock is assumed to have been running for 100usec prior to the removal of the reset signal, so that everything is stable. this is the same reset active time after clock is stable that is used for the pci bus. 2) when npci_reset goes active (low): a) the host drives the nlframe signal high, tristates the lad[3:0] signals, and ignores the nldrq signal. b) the lpc47n227 ignores nlframe, tri- states the lad[3:0] pins and drives the nldrq signal inactive (high). lpc transfers wait state requirements i/o transfers the lpc47n227 inserts three wait states for an i/o read and two wait states for an i/o write cycle. a sync of 0110 is used for all i/o transfers. the exception to this is for transfers where iochrdy would be deasserted in an isa transfer (i.e., epp or ircc transfers) in which case the sync pattern of 0110 is used and a large number of syncs may be inserted (up to 330 which corresponds to a timeout of 10us). dma transfers the lpc47n227 inserts three wait states for a dma read and four wait st ates for a dma write cycle. a sync of 0101 is used for all dma transfers. see the example timing for the lpc cycles in the ?timing diagrams? section.
22 floppy disk controller the floppy disk controller (fdc) provides the interface between a host microprocessor and the floppy disk drives. the fdc integrates the functions of the formatter/ controller, digital data separator, write precompens ation and data rate selection logic for an ibm xt/at compatible fdc. the true cmos 765b core guarantees 100% ibm pc xt/at compatibility in addition to providing data overflow and underflow protection. the fdc is compatible to the 82077aa using smsc's proprietary floppy disk controller core. the lpc47n227 supports one floppy disk drive directly through the fdc interface pins and two floppy disk drives via the fdc interface on the parallel port pins. it can also be configured to support one drive on the fdc interface pins and one drive on the parallel port pins. fdc internal registers the floppy disk controller contains eight internal registers that facilitate the interfacing between the host microprocessor and the disk drive. table 2 shows the addresses required to access these registers. registers other than the ones shown are not supported. the rest of the description assumes that the primary addresses have been selected. table 2 ? status, data and control registers (shown with base addresses of 3f0 and 370) primary address secondary address r/w register 3f0 3f1 3f2 3f3 3f4 3f4 3f5 3f6 3f7 3f7 370 371 372 373 374 374 375 376 377 377 r r r/w r/w r w r/w r w status register a (sra) status register b (srb) digital output register (dor) tape drive register (tdr) main status register (msr) data rate select register (dsr) data (fifo) reserved digital input register (dir) configuration contro l register (ccr) status register a (sra) address 3f0 read only this register is read-onl y and monitors the state of the internal interrupt signal and several disk interface pins in ps/2 and model 30 modes. the sra can be accessed at any time when in ps/2 mode. in the pc/at m ode the data bus pins d0 - d7 are held in a high impedance state for a read of address 3f0.
23 ps/2 mode 7 6 5 4 3 2 1 0 int pending ndrv2 step ntrk0 hdsel nindx nwp dir reset cond. 0 1 0 n/a 0 n/a n/a 0 bit 0 direction active high status indicating the di rection of head movement. a logic "1" indicates inward direction; a logic "0" indicates outward direction. bit 1 nwrite protect active low status of the write protect disk interfac e input. a logic "0" indicates that the disk is write protected. bit 2 nindex active low status of the index disk interface input. bit 3 head select active high status of the hdsel disk interface input. a logic "1" selects side 1 and a logic "0" selects side 0. bit 4 ntrack 0 active low status of the trk0 disk interface input. bit 5 step active high status of the step output disk interface output pin. bit 6 ndrv2 this function is not supported. this bit is always read as ?1?. bit 7 interrupt pending active high bit indicating the state of the floppy disk interrupt output. ps/2 model 30 mode 7 6 5 4 3 2 1 0 int pending drq step f/f trk0 nhdsel indx wp ndir reset cond. 0 0 0 n/a 1 n/a n/a 1 bit 0 ndirection active low status indicating the dire ction of head movement. a logic "0" i ndicates inward direction; a logic "1" indicates outward direction.
24 bit 1 write protect active high status of the write protect disk interfac e input. a logic "1" indicates that the disk is write protected. bit 2 index active high status of the index disk interface input. bit 3 nhead select active low status of the hdsel disk interface input. a logic "0" selects side 1 and a logic "1" selects side 0. bit 4 track 0 active high status of the trk0 disk interface input. bit 5 step active high status of the latched step disk interface out put pin. this bit is latched with the step output going active, and is cleared with a read from the dir register, or with a hardware or software reset. bit 6 dma request active high status of the dma request pending. bit 7 interrupt pending active high bit indicating the state of the floppy disk interrupt. status register b (srb) address 3f1 read only this register is read-only and monitors the state of several disk interfac e pins in ps/2 and model 30 modes. the srb can be accessed at any time when in ps/2 mode. in the pc/at mode the data bus pins d0 - d7 are held in a high impedance stat e for a read of address 3f1. ps/2 mode 7 6 5 4 3 2 1 0 1 1 drive sel0 wdata toggle rdata toggle wgate mot en1 mot en0 reset cond. 1 1 0 0 0 0 0 0 bit 0 motor enable 0 active high status of the mtr0 di sk interface output pin. this bi t is low after a hardware reset and unaffected by a software reset. bit 1 motor enable 1 active high status of the mtr1 di sk interface output pin. this bit is low after a hardware reset and unaffected by a software reset. bit 2 write gate active high status of the wgate disk interface output. bit 3 read data toggle
25 every inactive edge of the rdata input causes this bit to change state. bit 4 write data toggle every inactive edge of the wdata input causes this bit to change state. bit 5 drive select 0 reflects the status of the drive se lect 0 bit of the dor (address 3f2 bi t 0). this bit is cleared after a hardware reset and it is unaffected by a software reset. bit 6 reserved always read as a logic "1". bit 7 reserved always read as a logic "1". ps/2 model 30 mode 7 6 5 4 3 2 1 0 ndrv2 nds1 nds0 wdata f/f rdata f/f wgate f/f nds3 nds2 reset cond. n/a 1 1 0 0 0 1 1 bit 0 ndrive select 2 the ds2 disk interface is not supported. bit 1 ndrive select 3 the ds3 disk interface is not supported. bit 2 write gate active high status of the latched wg ate output signal. this bit is la tched by the active going edge of wgate and is cleared by the read of the dir register. bit 3 read data active high status of the latched rda ta output signal. this bit is latched by the inactive going edge of rdata and is cleared by the read of the dir register. bit 4 write data active high status of the latched wdat a output signal. this bit is latc hed by the inactive going edge of wdata and is cleared by the read of the dir regi ster. this bit is not gated with wgate. bit 5 ndrive select 0 active low status of the ds0 disk interface output. bit 6 ndrive select 1 active low status of the ds1 disk interface output. bit 7 ndrv2 active low status of the drv2 disk interface i nput. note: this function is not supported.
26 digital output register (dor) address 3f2 read/write the dor controls the drive select and motor enables of the disk inte rface outputs. it also contains the enable for the dma logic and a software reset bit. t he contents of the dor ar e unaffected by a software reset. the dor can be written to at any time. 7 6 5 4 3 2 1 0 mot en3 mot en2 mot en1 mot en0 dmaen nrese t drive sel1 drive sel0 reset cond. 0 0 0 0 0 0 0 0 bit 0 and 1 drive select these two bits are binary encoded for the drive select s, thereby allowing only one drive to be selected at one time. bit 2 nreset a logic "0" written to this bit resets the floppy disk contro ller. this reset will remain active until a logic "1" is written to this bit. this software reset does not affe ct the dsr and ccr registers, nor does it affect the other bits of the dor register. t he minimum reset duration required is 10 0ns, therefore toggling this bit by consecutive writes to this register is a valid method of issuing a software reset. bit 3 dmaen pc/at and model 30 mode: writing this bit to logic "1" will enable the dma and inte rrupt functions. this bit being a logic "0" will disable the dma and interrupt functions. this bit is a logic "0" after a reset and in these modes. ps/2 mode: in this mode the dma and interrupt functions are always enabled. during a reset, this bit will be cleared to a logic "0". bit 4 motor enable 0 this bit controls the mtr0 disk interface output. a logic "1" in this bit will cause the output pin to go active. bit 5 motor enable 1 this bit controls the mtr1 disk interface output. a logic "1" in this bit will cause the output pin to go active.
27 bit 6 motor enable 2 the mtr2 disk interface output is not supported. bit 7 motor enable 3 the mtr3 disk interface output is not supported. drive dor value 0 1 1ch 2dh table 3 ? internal 2 drive decode (normal) digital output register drive select outputs (active low) motor on outputs (active low) bit 5 bit 4 bit1 bit 0 nds1 nds0 nmtr1 nmtr0 x 1 0 0 1 0 nbit 5 nbit 4 1 x 0 1 0 1 nbit 5 nbit 4 0 0 x x 1 1 nbit 5 nbit 4 table 4 ? internal 2 drive decode (drives 0 and 1 swapped) digital output register drive select outputs (active low) motor on outputs (active low) bit 5 bit 4 bit1 bit 0 nds1 nds0 nmtr1 nmtr0 x 1 0 0 0 1 nbit 4 nbit 5 1 x 0 1 1 0 nbit 4 nbit 5 0 0 x x 1 1 nbit 4 nbit 5 tape drive register (tdr) address 3f3 read/write the tape drive register (tdr) is included for 82077 so ftware compatibility and allows the user to assign tape support to a particular drive duri ng initialization. any future refer ences to that drive automatically invokes tape support. the tdr tape select bits tdr .[1:0] determine the tape drive number. table 5 illustrates the tape select bit encoding. note that drive 0 is the boot device and cannot be assigned tape support. the remaining tape drive register bits tdr.[7:2] are tristated when read. the tdr is unaffected by a software reset. table 5 ? tape select bits tape sel1 (tdr.1) tape sel0 (tdr.0) drive selected 0 0 1 1 0 1 0 1 none 1 2 3 note: the lpc47n227 supports one floppy drive directly on the fdc interface pins and two floppy drives on the parallel port. normal floppy mode
28 normal mode. register 3f3 contains only bits 0 and 1. when this register is read, bits 2 - 7 are ?0?. db7 db6 db5 db4 db3 db2 db1 db0 reg 3f3 0 0 0 0 0 0 tape sel1 tape sel0 enhanced floppy mode 2 (os2) register 3f3 for enhanced floppy mode 2 operation. db7 db6 db5 db4 db3 db2 db1 db0 reg 3f3 reserved reserved drive type id floppy boot drive tape sel1 tape sel0 table 6 ? drive type id digital output register register 3f3 - drive type id bit 1 bit 0 bit 5 bit 4 0 0 cr06 - b1 cr06 - b0 0 1 cr06 - b3 cr06 - b2 1 0 cr06 - b5 cr06 - b4 1 1 cr06 - b7 cr06 - b6 note: cr06-bx = configuration register 06, bit x. data rate select register (dsr) address 3f4 write only this register is write only. it is used to program the data rate, amount of wr ite precompensation, power down status, and software reset. the data rate is pr ogrammed using the configur ation control register (ccr) not the dsr, for pc/at and ps/2 model 30 applications. other applic ations can set the data rate in the dsr. the data rate of the floppy controller is the most recent writ e of either the dsr or ccr. the dsr is unaffected by a software reset. a hardware reset will set the dsr to 02h, which corresponds to the default precompensation setting and 250 kbps. 7 6 5 4 3 2 1 0 s/w reset power down 0 pre- comp2 pre- comp1 pre- comp0 drate sel1 drate sel0 reset cond. 0 0 0 0 0 0 1 0 bit 0 and 1 data rate select these bits control the data rate of the floppy controller. see table 8 for the settings corresponding to the individual data rates. the data rate select bits are unaffected by a software reset, and are set to 250 kbps after a hardware reset. bit 2 through 4 precompensation select these three bits select the value of write precompensation that will be applied to the wdata output signal. table 7 shows the precompensation va lues for the combination of thes e bits settings. track 0 is the default starting track number to star t precompensation. this starting track number can be changed by the configure command.
29 bit 5 undefined should be written as a logic "0". bit 6 low power a logic "1" written to this bit will put the floppy cont roller into manual low power mode. the floppy controller clock and data separator circuits will be turned off. th e controller will come out of manual low power mode after a software reset or access to the da ta register or main status register. bit 7 software reset this active high bit has the same function as the dor reset (dor bit 2) except that this bit is self clearing. note: the dsr is shadowed in the floppy data rate select shadow register, located in the configuration section (cr14). table 7 ? precompensation delays precomp 432 precompensation delay (nsec) <2mbps 2mbps 111 001 010 011 100 101 110 000 0.00 41.67 83.34 125.00 166.67 208.33 250.00 default 0 20.8 41.7 62.5 83.3 104.2 125 default default: see table 10 table 8 ? data rates drive rate data rate data rate densel drate(1) drt1 drt0 sel1 sel0 mfm fm 1 0 0 0 1 1 1meg --- 1 1 1 0 0 0 0 500 250 1 0 0 0 0 0 1 300 150 0 0 1 0 0 1 0 250 125 0 1 0 0 1 1 1 1meg --- 1 1 1 0 1 0 0 500 250 1 0 0 0 1 0 1 500 250 0 0 1 0 1 1 0 250 125 0 1 0 1 0 1 1 1meg --- 1 1 1 1 0 0 0 500 250 1 0 0 1 0 0 1 2meg --- 0 0 1 1 0 1 0 250 125 0 1 0 drive rate table (recommended) 00 = 360k, 1.2m, 720k, 1.44m and 2.88m vertical format 01 = 3-mode drive 10 = 2 meg tape
30 note 1: the drate and densel val ues are mapped onto the drvden pins. table 9 ? drvden mapping0 dt1 dt0 drvden1 (1) drvden0 (1) drive type 0 0 drate0 densel 4/2/1 mb 3.5" 2/1 mb 5.25" fdds 2/1.6/1 mb 3.5" (3-mode) 1 0 drate0 drate1 0 1 drate0 ndensel ps/2 1 1 drate1 drate0 table 10 ? default precompensation delays data rate precompensatio n delays 2 mbps 1 mbps 500 kbps 300 kbps 250 kbps 20.8 ns 41.67 ns 125 ns 125 ns 125 ns main status register (msr) address 3f4 read only the main status register is a read- only register and indicates the stat us of the disk controller. the main status register can be read at any time. the msr i ndicates when the disk controller is ready to receive data via the data register. it should be read before ea ch byte transferring to or from the data register except in dma mode. no delay is required when reading the msr after a data transfer. 7 6 5 4 3 2 1 0 rqm dio non dma cmd busy reserved reserved drv1 busy drv0 busy bit 0 - 1 drv x busy these bits are set to 1s when a drive is in the seek portion of a command, including implied and overlapped seeks and recalibrates. bit 4 command busy this bit is set to a 1 when a command is in progress. this bit will go active after the command byte has been accepted and goes inactive at t he end of the results phase. if there is no result phase (seek, recalibrate commands), this bit is returned to a 0 a fter the last command byte. bit 5 non-dma this mode is selected in the specify command and w ill be set to a 1 during the execution phase of a command. this is for polled data transfers and helps differentiate between the data transfer phase and the reading of result bytes. bit 6 dio indicates the direction of a data trans fer once a rqm is set. a 1 indicates a read and a 0 indicates a write is required.
31
32 bit 7 rqm indicates that the host can transfer data if set to a 1. no access is permitted if set to a 0. data register (fifo) address 3f5 read/write all command parameter information, disk data and result status are transferred between the host processor and the floppy disk controller through the data register. data transfers are governed by the rqm and dio bits in the main status register. the data register defaults to fifo disabled mode a fter any form of reset. this maintains pc/at hardware compatibility. the default values can be changed through the configure command (enable full fifo operation with threshold control). t he advantage of the fifo is that it allows t he system a larger dma latency without causing a disk error. table 11 give s several examples of the delays with a fifo. the data is based upon the following formula: threshold # x 1 data rate x 8 - 1.5 s = delay at the start of a command, the fi fo action is always disabled a nd command parameters are sent based upon the rqm and dio bit settings. as the command exec ution phase is entered, th e fifo is cleared of any data to ensure that inva lid data is not transferred. an overrun or underrun will terminate the current co mmand and the transfer of data. disk writes will complete the current sector by generating a 00 pattern and valid crc. reads require the host to remove the remaining data so that the result phase may be entered. table 11 ? fifo service delay fifo threshold examples maximum delay to servicing at 2 mbps data rate 1 byte 2 bytes 8 bytes 15 bytes 1 x 4 s - 1.5 s = 2.5 s 2 x 4 s - 1.5 s = 6.5 s 8 x 4 s - 1.5 s = 30.5 s 15 x 4 s - 1.5 s = 58.5 s fifo threshold examples maximum delay to servicing at 1 mbps data rate 1 byte 2 bytes 8 bytes 15 bytes 1 x 8 s - 1.5 s = 6.5 s 2 x 8 s - 1.5 s = 14.5 s 8 x 8 s - 1.5 s = 62.5 s 15 x 8 s - 1.5 s = 118.5 s
33 fifo threshold examples maximum delay to servicing at 500 kbps data rate 1 byte 2 bytes 8 bytes 15 bytes 1 x 16 s - 1.5 s = 14.5 s 2 x 16 s - 1.5 s = 30.5 s 8 x 16 s - 1.5 s = 126.5 s 15 x 16 s - 1.5 s = 238.5 s digital input register (dir) address 3f7 read only this register is read-only in all modes. pc-at mode 7 6 5 4 3 2 1 0 dsk chg 0 0 0 0 0 0 0 reset cond. n/a n/a n/a n/a n/a n/a n/a n/a bit 0 - 6 undefined the data bus outputs d0 - 6 are read as ?0?. bit 7 dskchg this bit monitors the pin of the same name and refl ects the opposite value seen on the disk cable or the value programmed in the force fdd status change register (cr17). see the configuration section for register description. ps/2 mode 7 6 5 4 3 2 1 0 dsk chg 1 1 1 1 drate sel1 drate sel0 nhigh ndens reset cond. n/a n/a n/a n/a n/a n/a n/a 1 bit 0 nhigh dens this bit is low whenever the 500 kbps or 1 mbps data rates are selected, and high when 250 kbps and 300 kbps are selected. bits 1 - 2 data rate select these bits control the data rate of the floppy controller. see table 8 for the settings corresponding to the individual data rates. the data rate select bits are unaffected by a software reset, and are set to 250 kbps after a hardware reset. bits 3 - 6 undefined always read as a logic "1"
34 bit 7 dskchg this bit monitors the pin of the same name and refl ects the opposite value seen on the disk cable or the value programmed in the force disk change register (cr 17). see the configurati on section for register description. model 30 mode 7 6 5 4 3 2 1 0 dsk chg 0 0 0 dmaen noprec drate sel1 drate sel0 reset cond. n/a 0 0 0 0 0 1 0 bits 0 - 1 data rate select these bits control the data rate of the floppy controller. see table 8 for the settings corresponding to the individual data rates. the data rate select bits are unaffected by a software reset, and are set to 250 kbps after a hardware reset. bit 2 noprec this bit reflects the value of noprec bit set in the ccr register. bit 3 dmaen this bit reflects the value of dmaen bit set in the dor register bit 3. bits 4 - 6 undefined always read as a logic "0" bit 7 dskchg this bit monitors the pin of the same name and refl ects the opposite value s een on the disk cable or the value programmed in the force disk change register ( cr17). see the configurat ion section for register description. configuration contro l register (ccr) address 3f7 write only pc/at and ps/2 modes 7 6 5 4 3 2 1 0 0 0 0 0 0 0 drate sel1 drate sel0 reset cond. n/a n/a n/a n/a n/a n/a 1 0 bit 0 and 1 data rate select 0 and 1 these bits determine the data rate of the floppy co ntroller. see table 8 for the appropriate values. bit 2 - 7 reserved should be set to a logical "0".
35 ps/2 model 30 mode 7 6 5 4 3 2 1 0 0 0 0 0 0 noprec drate sel1 drate sel0 reset cond. n/a n/a n/a n/a n/a n/a 1 0 bit 0 and 1 data rate select 0 and 1 these bits determine the data rate of the floppy c ontroller. see table 8 for the appropriate values. bit 2 no precompensation this bit can be set by software, but it has no functiona lity. it can be read by bit 2 of the dsr when in model 30 register mode. unaffected by software reset. bit 3 - 7 reserved should be set to a logical "0" table 9 shows the state of the densel pin. the de nsel pin is set high after a hardware reset and is unaffected by the dor and the dsr resets. status register encoding during the result phase of certain co mmands, the data register contains dat a bytes that give the status of the command just executed. table 12 ? status register 0 bit no. symbol name description 7,6 ic interrupt code 00 - normal te rmination of command. the specified command was properly exec uted and completed without error. 01 - abnormal termination of command. command execution was started, but was not successfully completed. 10 - invalid command. the requested command could not be executed. 11 - abnormal termination caused by polling. 5 se seek end the fdc completed a seek, relative seek or recalibrate command (used during a sense interrupt command). 4 ec equipment check the trk0 pin failed to become a "1" after: 1. 80 step pulses in the recalibrate command. 2. the relative seek command caused the fdc to step outward beyond track 0. 3 unused. this bit is always "0". 2 h head address the current head address. 1,0 ds1,0 drive select t he current selected drive.
36 table 13 ? status register 1 bit no. symbol name description 7 en end of cylinder the fdc tried to access a sector beyond the final sector of the track (255d). will be set if tc is not issued after read or write data command. 6 unused. this bit is always "0". 5 de data error the fdc detected a crc error in either the id field or the data field of a sector. 4 or overrun/ underrun becomes set if the fdc does not receive cpu or dma service within the required time interval, resulting in data overrun or underrun. 3 unused. this bit is always "0". 2 nd no data any one of the following: 1. read data, read deleted data command - the fdc did not find the specified sector. 2. read id command - the fdc cannot read the id field without an error. 3. read a track command - the fdc cannot find the proper sector sequence. 1 nw not writeable wp pin became a "1 " while the fdc is executing a write data, write deleted data, or format a track command. 0 ma missing address mark any one of the following: 1. the fdc did not detect an id address mark at the specified track after encountering the index pulse from the nindex pin twice. 2. the fdc cannot detect a data address mark or a deleted data address mark on the specified track.
37 table 14 ? status register 2 bit no. symbol name description 7 unused. this bit is always "0". 6 cm control mark any one of the following: read data command - the fdc encountered a deleted data address mark. read deleted data command - the fdc encountered a data address mark. 5 dd data error in data field the fdc detected a crc error in the data field. 4 wc wrong cylinder the track address from the sector id field is different from the track address maintained inside the fdc. 3 unused. this bit is always "0". 2 unused. this bit is always "0". 1 bc bad cylinder the track address from the sector id field is different from the track address maintained inside the fdc and is equal to ff hex, which indicates a bad track with a hard error according to the ibm soft-sectored format. 0 md missing data address mark the fdc cannot detect a data address mark or a deleted data address mark. table 15 ? status register 3 bit no. symbol name description 7 unused. this bit is always "0". 6 wp write protected indicates the status of the wrtprt pin. 5 unused. this bit is always "1". 4 t0 track 0 indicates the status of the trk0 pin. 3 unused. this bit is always "1". 2 hd head address indicates the status of the hdsel pin. 1,0 ds1,0 drive select indicates t he status of the ds1, ds0 pins. reset there are three sources of system reset on the f dc: the npci_reset pin, a reset generated via a bit in the dor, and a reset generated via a bit in the dsr. at power on, a powe r on reset initializes the fdc. all resets take the fdc out of the power down state. all operations are terminated upon a npci _reset, and the fdc enters an idle state. a reset while a disk write is in progress w ill corrupt the data and crc. on exiting the reset state, various internal r egisters are cleared, includi ng the configure command information, and the fdc waits for a new command. drive polling will start unless disabled by a new configure command.
38 npci_reset pin (hardware reset) the npci_reset pin is a global reset and clears all registers except those pr ogrammed by the specify command. the dor reset bit is enabled and must be cleared by the host to exit the reset state. dor reset vs. dsr reset (software reset) these two resets are functionally the same. both w ill reset the fdc core, which affects drive status information and the fifo circuits. the dsr reset clears itself automatically wh ile the dor reset requires the host to manually clear it. dor reset has prec edence over the dsr reset. the dor reset is set automatically upon a pin reset. the user must manually clear this reset bit in th e dor to exit the reset state. modes of operation the fdc has three modes of operation, pc/at mode, ps/2 mode and model 30 mode. these are determined by the state of the interface mode bits (mfm and ident) in cr03[5,6]. pc/at mode the pc/at register set is enabled, the dma enable bit of the dor becomes valid (controls the interrupt and dma functions), and densel is an active high signal. ps/2 mode this mode supports the ps/2 models 50 /60/80 configuration an d register set. the dma bit of the dor becomes a "don't care". the dma and interrupt functi ons are always enabled, and densel is active low. model 30 mode this mode supports ps/2 model 30 configuration and register set. the dma enable bit of the dor becomes valid (controls the interrupt and dm a functions), and densel is active low. dma transfers dma transfers are enabled with the specify command a nd are initiated by the fdc by activating a dma request cycle. dma read, write and verify cycles are supported. the fdc supports two dma transfer modes: single transfer and burst transfer. burst mode is enabled via cr05-bit[2]. see the configuration section. controller phases for simplicity, command handling in the fdc can be divided into three phases : command, execution, and result. each phase is describ ed in the following sections. command phase after a reset, the fdc enters the command phase and is ready to accept a command from the host. for each of the commands, a defined se t of command code bytes and parameter bytes has to be written to the fdc before the command phase is complete. (please refe r to table 16 for the command set descriptions). these bytes of data must be trans ferred in the order prescribed. before writing to the fdc, the host must examine t he rqm and dio bits of the main status register. rqm and dio must be equal to "1" and "0" respective ly before command bytes may be written. rqm is set false by the fdc after each write cycle until the received byte is processed. the fdc asserts rqm again to request each parameter byte of the comma nd unless an illegal command condition is detected. after the last parameter byte is received, rqm re mains "0" and the fdc automat ically enters the next phase as defined by the command definition.
39 the fifo is disabled during the command phase to provide for the proper hand ling of the "invalid command" condition. execution phase all data transfers to or from the fdc occur during the execution phase, which can proceed in dma or non- dma mode as indicated in the specify command. after a reset, the fifo is disabled. each data by te is transferred by a read/ write or dma cycle depending on the dma mode. the configure command can enabl e the fifo and set the fifo threshold value. the following paragraphs detail the operation of the fifo fl ow control. in these descriptions, is defined as the number of bytes ava ilable to the fdc when service is requested from the host and ranges from 1 to 16. the parameter fifothr, which the user programs, is one less and ranges from 0 to 15. a low threshold value (i.e. 2) results in longer periods of time between service r equests, but requires faster servicing of the request for both read and write cases. the host reads (writes) from (to) the fifo until empty (full), then the transfer reques t goes inactive. the host must be very responsive to the service request. this is the desired case for use with a "fast" system. a high value of threshold (i.e. 12) is used with a "sl uggish" system by affording a long latency period after a service request, but results in more frequent service requests. non-dma mode - transfers from the fifo to the host the interrupt and rqm bit in the ma in status register are activa ted when the fifo contains (16- ) bytes or the last bytes of a full sect or have been placed in the fifo. the interrupt can be used for interrupt-driven systems, and rqm can be used for polled systems. the host must respond to the request by reading data from the fifo. this process is repeated until the last byte is transferred out of the fifo. the fdc will deactivate the interrupt and rqm bit when the fifo becomes empty. non-dma mode - transfers from the host to the fifo the interrupt and rqm bit in the main status regist er are activated upon enteri ng the execution phase of data transfer commands. the host must respond to the reques t by writing data into the fifo. the interrupt and rqm bit remain true until the fifo becomes full. they are set true again when the fifo has bytes remaining in the fifo. the fdc ente rs the result phase after the last byte is taken by the fdc from the fifo (i.e. fifo empty condition). dma mode - transfers from the fifo to the host the fdc generates a dma request cycle when the fifo co ntains (16 - ) by tes, or the last byte of a full sector transfer has been placed in the fi fo. the dma controller responds to the request by reading data from the fifo. the f dc will deactivate the dma request when the fifo becomes empty by generating the proper sync for the data transfer. dma mode - transfers from the host to the fifo. the fdc generates a dma request cycle when enter ing the execution phase of the data transfer commands. the dma controller responds by placing da ta in the fifo. the dma request remains active until the fifo becomes full. the dm a request cycle is reasserted when the fifo has bytes
40 remaining in the fifo. the fdc will terminate the dma cycle after a tc, indicating that no more data is required. data transfer termination the fdc supports terminal count explicitly thr ough the tc cycle and implicitly through the underrun/overrun and end-of-track (eot) functions. for full sector transfers, the eot parameter can define the last sector to be transferred in a single or multi-sector transfer. if the last sector to be transferr ed is a partial sector, the host can st op transferring the data in mid-sector, and the fdc will continue to complete the sector as if a tc cycle was received. the only difference between these implicit functi ons and tc cycle is that they return " abnormal termination" result status. such status indications can be ignor ed if they were expected. note that when the host is sending dat a to the fifo of the fdc, the inte rnal sector count will be complete when the fdc reads the last byte from its side of the fifo. there may be a delay in the removal of the transfer request signal of up to the time taken for t he fdc to read the last 16 bytes from the fifo. the host must tolerate this delay. result phase the generation of the interr upt determines the beginning of the result phase. for each of the commands, a defined set of result bytes has to be read from the fdc before the result phase is complete. these bytes of data must be read out for another command to start. rqm and dio must both equal "1" before the result byte s may be read. after all th e result bytes have been read, the rqm and dio bits switch to "1" and "0" respec tively, and the cb bit is cleared, indicating that the fdc is ready to accept the next command. command set/descriptions commands can be written whenever the fdc is in the command phase. each command has a unique set of needed parameters and status resu lts. the fdc checks to see t hat the first byte is a valid command and, if valid, proceeds with the command. if it is invalid, an interrupt is issued. the user sends a sense interrupt status command which retu rns an invalid command error. refer to table 16 for explanations of the various sy mbols used. table 17 lists the required parameters and the results associated with each command that the fdc is capable of performing. table 16 ? description of command symbols symbol name description c cylinder address the currently selected address; 0 to 255. d data pattern the pattern to be written in each sector data field during formatting. d0, d1 drive select 0-1 designates which drives are perpendicul ar drives on the perpendicular mode command. a "1" indicates a perpendicular drive. dir direction control if this bit is 0, then the head will step out from the spindle during a relative seek. if set to a 1, the head will step in toward the spindle. ds0, ds1 disk drive select ds1 ds0 drive 0 0 drive 0 0 1 drive 1
41 symbol name description dtl special sector size by setting n to zero (00), dtl ma y be used to control the number of bytes transferred in disk read/write commands. the sector size (n = 0) is set to 128. if the actual se ctor (on the diskette) is larger than dtl, the remainder of the actual se ctor is read but is not passed to the host during read commands; during write commands, the remainder of the actual sector is wr itten with all zero bytes. the crc check code is calculated with the ac tual sector. when n is not zero, dtl has no meaning and should be set to ff hex. ec enable count when this bit is "1" t he "dtl" parameter of the verify command becomes sc (number of sectors per track). efifo enable fifo this active low bit when a 0, enables the fifo. a "1" disables the fifo (default). eis enable implied seek when set, a seek operation will be performed before executing any read or write command that requi res the c parameter in the command phase. a "0" disables the implied seek. eot end of track the final sector number of the current track. gap alters gap 2 length when using perpendicular mode. gpl gap length the gap 3 size. (gap 3 is the space between se ctors excluding the vco synchronization field). h/hds head address selected head: 0 or 1 (di sk side 0 or 1) as encoded in the sector id field. hlt head load time the time interval that fdc waits after loading the head and before initializing a read or write operation. refer to the specify command for actual delays. hut head unload time the time interval from the end of the execut ion phase (of a read or write command) until the head is unloaded. refer to the specify command for actual delays. lock lock defines whether efifo, fi fothr, and pretrk parameters of the configure command can be reset to their default values by a "software reset". (a reset caused by writing to the appropriate bits of either the dsr or dor) mfm mfm/fm mode selector a one selects the double density (mfm) mode. a zero selects single density (fm) mode. mt multi-track selector when set, this flag selects the mult i-track operating mode. in this mode, the fdc treats a complete cylinder under head 0 and 1 as a single track. the fdc operates as this expanded track started at the first sector under head 0 and ended at the last sector under head 1. with this flag set, a multitrack read or write operation will automatically continue to the firs t sector under head 1 when the fdc finishes operating on the last sector under head 0.
42 symbol name description n sector size code this specifies the number of bytes in a sector. if this parameter is "00", then the sector size is 128 bytes. the number of bytes transferred is determined by the dt l parameter. otherwise the sector size is (2 raised to the "n'th" power) times 128. all values up to "07" hex are allowable. "07"h would equal a sector size of 16k. it is the user's responsibility to not select combinations that are not possible with the drive. n sector size 00 128 bytes 01 256 bytes 02 512 bytes 03 1024 bytes ? ? 07 16k bytes ncn new cylinder number the desired cylinder number. nd non-dma mode flag when set to 1, indicates that t he fdc is to operate in the non-dma mode. in this mode, the host is interrupted for each data transfer. when set to 0, the fdc operates in dma mode. ow overwrite the bits d0-d3 of t he perpendicular mode command can only be modified if ow is set to 1. ow id defined in the lock command. pcn present cylinder number the current position of the head at the completion of sense interrupt status command. poll polling disable when set, the internal polli ng routine is disabled. when clear, polling is enabled. pretrk precompensation start track number programmable from track 00 to ffh. r sector address the sector number to be read or written. in multi-sector transfers, this parameter specifies the sector number of the first sector to be read or written. rcn relative cylinder number relative cylinder offset from present cylinder as used by the relative seek command. sc number of sectors per track the number of sectors per track to be initialized by the format command. the number of sectors per track to be verified during a verify command when ec is set. sk skip flag when set to 1, sectors containing a deleted data address mark will automatically be skipped during the execution of read data. if read deleted is executed, only sectors with a deleted address mark will be accessed. when set to "0", the sect or is read or written the same as the read and write commands. srt step rate interval the time interval between step pulses issued by the fdc. programmable from 0.5 to 8 millisec onds in increments of 0.5 ms at the 1 mbit data rate. refer to the specify command for actual delays.
43 symbol name description st0 st1 st2 st3 status 0 status 1 status 2 status 3 registers within the fdc which store status information after a command has been executed. this stat us information is available to the host during the result phas e after command execution. wgate write gate alters timing of we to allow for pre-erase loads in perpendicular drives. instruction set table 17 ? instruction set read data data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w mt mfm sk 0 0 1 1 0 command codes w 0 0 0 0 0 hds ds1 ds0 w c sector id information prior to command execution. w h w r w n w eot w gpl w dtl execution data transfer between the fdd and system. result r st0 status information after com- mand execution. r st1 r st2 r c sector id in formation after command execution. r h r r r n
44 read deleted data data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w mt mfm sk 0 1 1 0 0 command codes w 0 0 0 0 0 hds ds1 ds0 w c sector id information prior to command execution. w h w r w n w eot w gpl w dtl execution data transfer between the fdd and system. result r st0 status information after com- mand execution. r st1 r st2 r c sector id in formation after command execution. r h r r r n
45 write data data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w mt mfm 0 0 0 1 0 1 command codes w 0 0 0 0 0 hds ds1 ds0 w c sector id information prior to command execution. w h w r w n w eot w gpl w dtl execution data transfer between the fdd and system. result r st0 status information after com- mand execution. r st1 r st2 r c sector id in formation after command execution. r h r r r n
46 write deleted data data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w mt mfm 0 0 1 0 0 1 command codes w 0 0 0 0 0 hds ds1 ds0 w c sector id information prior to command execution. w h w r w n w eot w gpl w dtl execution data transfer between the fdd and system. result r st0 status information after command execution. r st1 r st2 r c sector id information after command execution. r h r r r n
47 read a track data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 mfm 0 0 0 0 1 0 command codes w 0 0 0 0 0 hds ds1 ds0 w c sector id information prior to command execution. w h w r w n w eot w gpl w dtl execution data transfer between the fdd and system. fdc reads all of cylinders' contents from index hole to eot. result r st0 status information after command execution. r st1 r st2 r c sector id information after command execution. r h r r r n
48 verify data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w mt mfm sk 1 0 1 1 0 command codes w ec 0 0 0 0 hds ds1 ds0 w c sector id information prior to command execution. w h w r w n w eot w gpl w dtl/sc execution no data transfer takes place. result r st0 status information after command execution. r st1 r st2 r c sector id information after command execution. r h r r r n version data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 1 0 0 0 0 command code result r 1 0 0 1 0 0 0 0 enhanced controller
49 format a track data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 mfm 0 0 1 1 0 1 command codes w 0 0 0 0 0 hds ds1 ds0 w n bytes/sector w sc sectors/cylinder w gpl gap 3 w d filler byte execution for each sector repeat: w c input sector parameters w h w r w n fdc formats an entire cylinder result r st0 status information after command execution r st1 r st2 r undefined r undefined r undefined r undefined
50 recalibrate data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 0 0 1 1 1 command codes w 0 0 0 0 0 0 ds1 ds0 execution head retracted to track 0 interrupt. sense interrupt status data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 0 1 0 0 0 command codes result r st0 status information at the end of each seek operation. r pcn specify data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 0 0 0 1 1 command codes w srt hut w hlt nd
51 sense drive status data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 0 0 1 0 0 command codes w 0 0 0 0 0 hds ds1 ds0 result r st3 status information about fdd seek data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 0 1 1 1 1 command codes w 0 0 0 0 0 hds ds1 ds0 w ncn execution head positioned over proper cylinder on diskette. configure data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 1 0 0 1 1 configure information w 0 0 0 0 0 0 0 0 w 0 eis efifo poll fifothr execution w pretrk
52 relative seek data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 1 dir 0 0 1 1 1 1 w 0 0 0 0 0 hds ds1 ds0 w rcn dumpreg data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 0 1 1 1 0 *note: registers placed in fifo execution result r pcn-drive 0 r pcn-drive 1 r pcn-drive 2 r pcn-drive 3 r srt hut r hlt nd r sc/eot r lock 0 d3 d2 d1 d0 gap wgate r 0 eis efifo poll fifothr r pretrk
53 read id data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 mfm 0 0 1 0 1 0 commands w 0 0 0 0 0 hds ds1 ds0 execution the first correct id information on the cylinder is stored in data register result r r r r r r r st0 st1 st2 c h r n status information after command execution.
54 perpendicular mode data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 1 0 0 1 0 command codes ow 0 d3 d2 d1 d0 gap wgate invalid codes data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w invalid codes invalid command codes (noop - fdc goes into stand- by state) result r st0 st0 = 80h lock data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w lock 0 0 1 0 1 0 0 command codes result r 0 0 0 lock 0 0 0 0 sc is returned if the last command that was issued wa s the format command. eot is returned if the last command was a read or write. note: these bits are used internally only. they are not reflected in the drive sele ct pins. it is the user's responsibility to maintain correspondence between t hese bits and the drive select pins (dor).
55 data transfer commands all of the read data, write data and verify type co mmands use the same paramet er bytes and return the same results information, the only difference being the coding of bits 0-4 in the first byte. an implied seek will be executed if the feature was enabled by the co nfigure command. this seek is completely transparent to the user. the drive busy bi t for the drive will go active in the main status register during the seek portion of the command. if the seek portion fails, it is reflected in the results status normally returned for a read/write data command. stat us register 0 (st0) would contain the error code and c would contain the cylinder on which the seek failed. read data a set of nine (9) bytes is required to place the fdc in the read data mode. after the read data command has been issued, the fdc loads the head (if it is in the unloaded state) , waits the specified head settling time (defined in the specify comm and), and begins reading id address marks and id fields. when the sector address read off the diskette matches with t he sector address specified in the command, the fdc reads the sector's data field and tr ansfers the data to the fifo. after completion of the read operation from the current sector, the sector addre ss is incremented by one and the data from the next logical sect or is read and output via the fifo. this continuous read function is called "multi-sector read operation". upon receip t of the tc cycle, or an implied tc (fifo overrun/underrun), the fdc stops sendi ng data but will continue to read data from the current sector, check the crc bytes, and at the end of the se ctor, terminate the read data command. n determines the number of bytes per se ctor (see table 18 below). if n is se t to zero, the sector size is set to 128. the dtl value determines t he number of bytes to be transferred. if dtl is less than 128, the fdc transfers the specified number of bytes to the host. for reads, it continues to read the entire 128-byte sector and checks for crc errors. for writ es, it completes the 128-byte sector by filling in zeros. if n is not set to 00 hex, dtl should be set to ff hex and has no impact on the number of bytes transferred. table 18 ? sector sizes n sector size 00 01 02 03 .. 07 128 bytes 256 bytes 512 bytes 1024 bytes ... 16 kbytes the amount of data which can be handled with a single command to the fdc depends upon mt (multi- track) and n (number of bytes/sector). the multi-track function (mt) allows the fdc to read data from both sides of the diskette. for a particular cylinder, data will be transferred starting at sector 1, side 0 and comple ting the last sector of the same track at side 1. if the host terminates a read or write operation in the fdc, the id in formation in the result phase is dependent upon the state of the mt bit and eot byte. refer to table 19.
56 at the completion of the read data command, t he head is not unloaded until after the head unload time interval (specified in the specify command) has elapsed. if the host issues anot her command before the head unloads, then the head settling time may be saved between subsequent reads. if the fdc detects a pulse on the ni ndex pin twice without finding the s pecified sector (meaning that the diskette's index hole passes through index detect logic in the drive twice), the fdc sets the ic code in status register 0 to "01" indicating abnormal terminat ion, sets the nd bit in status register 1 to "1" indicating a sector not found, and terminates the read data command. after reading the id and data fields in each sect or, the fdc checks the crc bytes. if a crc error occurs in the id or data field, t he fdc sets the ic code in status r egister 0 to "01" indicating abnormal termination, sets the de bit flag in st atus register 1 to "1", sets the dd bit in status register 2 to "1" if crc is incorrect in the id field, and terminates t he read data command. table 20 describes the effect of the sk bit on the read data command execution and results. except where noted in table 20, the c or r value of the sector address is automatically increm ented (see table 22) table 19 - effects of mt and n bits mt n maximum transfer capacity final sector read from disk 0 1 0 1 0 1 1 1 2 2 3 3 256 x 26 = 6,656 256 x 52 = 13,312 512 x 15 = 7,680 512 x 30 = 15,360 1024 x 8 = 8,192 1024 x 16 = 16,384 26 at side 0 or 1 26 at side 1 15 at side 0 or 1 15 at side 1 8 at side 0 or 1 16 at side 1 table 20 ? skip bit vs read data command sk bit value data address mark type encountered results sector read? cm bit of st2 set? description of results 0 normal data yes no normal termination. 0 deleted data yes yes address not incremented. next sector not searched for. 1 normal data yes no normal termination. 1 deleted data no yes normal termination. sector not read ("skipped").
57 read deleted data this command is the same as the read data command, only it operates on sectors that contain a deleted data address mark at the beginning of a data field. table 21 describes the effect of the sk bit on the read deleted data command execution and results. except where noted in table 21, the c or r value of the sector address is automatically incremented (see table 22). table 21 - skip bit vs. r ead deleted data command sk bit value data address mark type encountered results sector read? cm bit of st2 set? description of results 0 0 1 1 normal data deleted data normal data deleted data yes yes no yes yes no yes no address not incremented. next sector not searched for. normal termination. normal termination. sector not read ("skipped"). normal termination. read a track this command is similar to the read data command exce pt that the entire data fi eld is read continuously from each of the sectors of a tra ck. immediately after encountering a pulse on the nindex pin, the fdc starts to read all data fields on t he track as continuous blocks of data without regard to logical sector numbers. if the fdc finds an error in the id or data crc check bytes, it conti nues to read data from the track and sets the appropriate error bits at the end of the command. the fdc compares the id information read from each sector with the specif ied value in the command and sets t he nd flag of status register 1 to a ?1? if there no comparison. multi-track or skip operations are not allowed with this command. the mt and sk bits (bits d7 and d5 of the first command by te respectively) should always be set to "0". this command terminates when the eot specified numbe r of sectors has not been read. if the fdc does not find an id address mark on the diskette after th e second occurrence of a pulse on the nindex pin, then it sets the ic code in status register 0 to "01" (abnormal te rmination), sets the ma bit in status register 1 to "1", and terminates the command.
58 table 22 - result phase table mt head final sector transferred to id information at result phase host c h r n 0 0 less than eot nc nc r + 1 nc equal to eot c + 1 nc 01 nc 1 less than eot nc nc r + 1 nc equal to eot c + 1 nc 01 nc 1 0 less than eot nc nc r + 1 nc equal to eot nc lsb 01 nc 1 less than eot nc nc r + 1 nc equal to eot c + 1 lsb 01 nc nc: no change, the same value as the one at the beginning of command execution. lsb: least significant bit, the lsb of h is complemented. write data after the write data command has be en issued, the fdc loads the head (i f it is in the unloaded state), waits the specified head load time if unloaded ( defined in the specify command), and begins reading id fields. when the sector address read from the diske tte matches the sector address specified in the command, the fdc reads the data from the host via the fifo and writes it to the sector's data field. after writing data into the current sector, the fdc computes the crc val ue and writes it into the crc field at the end of the sector transfer. the sector number stored in "r" is incremented by one, and the fdc continues writing to the next data field. the fdc continues this "m ulti-sector write operation". upon receipt of a terminal count signal or if a fifo over/under run occurs while a data field is being written, then the remainder of the data field is f illed with zeros. the fdc reads t he id field of each sector and checks the crc bytes. if it detects a crc error in one of the id fields, it sets th e ic code in status register 0 to "01" (abnormal termination), sets the de bit of status register 1 to "1", and terminates the write data command. the write data command operates in much the same manner as the read data command. the following items are the same. please refer to the read data command for details: transfer capacity en (end of cylinder) bit nd (no data) bit head load, unload time interval id information when the host terminates the command definition of dtl when n = 0 and when n does not = 0 write deleted data this command is almost the same as the write data command except that a de leted data address mark is written at the beginning of the data field instead of the normal data address mark. this command is typically used to mark a bad sector containing an error on the floppy disk.
59 verify the verify command is used to verify the data stor ed on a disk. this command acts exactly like a read data command except that no data is transferred to the host. data is read from the disk and crc is computed and checked against the previously-stored value. because data is not transferred to the host, the tc cycle cannot be used to terminate this command. by setting the ec bit to "1", an implicit tc will be issued to the fdc. this implicit tc will occur when the sc value has decremented to 0 (an sc value of 0 will verify 256 sectors). this command can also be terminated by setting the ec bit to "0" and the eot value equal to the final sector to be checked. if ec is set to "0", dtl/sc should be programmed to 0ffh . refer to table 22 and table 23 for information concerning the values of mt a nd ec versus sc and eot value. definitions: # sectors per side = number of formatte d sectors per each side of the disk. # sectors remaining = number of formatted sectors left which can be read, includi ng side 1 of the disk if mt is set to "1".
60 table 23 ? verify command result phase table mt ec sc/eot value termination result 0 0 sc = dtl eot <= # sectors per side success termination result phase valid 0 0 sc = dtl eot > # sectors per side unsuccessful termination result phase invalid 0 1 sc <= # sectors remaining and eot <= # sectors per side successful termination result phase valid 0 1 sc > # sectors remaining or eot > # sectors per side unsuccessful termination result phase invalid 1 0 sc = dtl eot <= # sectors per side successful termination result phase valid 1 0 sc = dtl eot > # sectors per side unsuccessful termination result phase invalid 1 1 sc <= # sectors remaining and eot <= # sectors per side successful termination result phase valid 1 1 sc > # sectors remaining or eot > # sectors per side unsuccessful termination result phase invalid note: if mt is set to "1" and the sc value is gr eater than the number of re maining formatted sectors on side 0, verifying will continue on side 1 of the disk. format a track the format command allows an entire track to be formatted. after a pulse from the nindex pin is detected, the fdc starts writing data on the disk including gaps, addr ess marks, id fields, and data fields per the ibm system 34 or 3740 format (mfm or fm respecti vely). the particular va lues that will be written to the gap and data field are controlled by the values programmed into n, sc, gpl, and d which are specified by the host during the command phase. the data field of the se ctor is filled with the data byte specified by d. the id field for eac h sector is supplied by the host; that is, four data bytes per sector are needed by the fdc for c, h, r, and n (cylinder, head, sector number and sector size respectively). after formatting each sector, the host must send new val ues for c, h, r and n to the fdc for the next sector on the track. the r value (sector number) is the only value that must be changed by the host after each sector is formatted. this allows the di sk to be formatted with nonsequential sector addresses (interleaving). this incrementi ng and formatting continues for the whole track until the fdc encounters a pulse on the nindex pin again and it terminates the command. table 24 contains typical values for gap fields which are dependent upon the size of the sector and the number of sectors on each track. actual va lues can vary due to drive electronics.
61 format fields system 34 (double density) format gap4a 80x 4e sync 12x 00 iam gap1 50x 4e sync 12x 00 idam c y l h d s e c n o c r c gap2 22x 4e sync 12x 00 data am data c r c gap3 gap 4b 3x c2 fc 3x a1 fe 3x a1 fb f8 system 3740 (single density) format gap4a 40x ff sync 6x 00 iam gap1 26x ff sync 6x 00 idam c y l h d s e c n o c r c gap2 11x ff sync 6x 00 data am data c r c gap3 gap 4b fc fe fb or f8 perpendicular format gap4a 80x 4e sync 12x 00 iam gap1 50x 4e sync 12x 00 idam c y l h d s e c n o c r c gap2 41x 4e sync 12x 00 data am data c r c gap3 gap 4b 3x c2 fc 3x a1 fe 3x a1 fb f8
62 table 24 ? typical values for formatting format sector size n sc gpl1 gpl2 5.25" drives fm 128 128 512 1024 2048 4096 ... 00 00 02 03 04 05 ... 12 10 08 04 02 01 07 10 18 46 c8 c8 09 19 30 87 ff ff mfm 256 256 512* 1024 2048 4096 ... 01 01 02 03 04 05 ... 12 10 09 04 02 01 0a 20 2a 80 c8 c8 0c 32 50 f0 ff ff 3.5" drives fm 128 256 512 0 1 2 0f 09 05 07 0f 1b 1b 2a 3a mfm 256 512** 1024 1 2 3 0f 09 05 0e 1b 35 36 54 74 gpl1 = suggested gpl values in read and write commands to avoid splice point between data field and id fiel d of contiguous sections. gpl2 = suggested gpl value in format a track command. *pc/at values (typical) **ps/2 values (typical). applies with 1.0 mb and 2.0 mb drives. note: all values except sector size are in hex.
63 control commands control commands differ from the other commands in that no data transfer take s place. three commands generate an interrupt when complete: read id, recalib rate, and seek. the other control commands do not generate an interrupt. read id the read id command is used to find the present position of the recording heads. the fdc stores the values from the first id field it is able to read into its registers. if the fdc does not find an id address mark on the diskette after the second occurrence of a pulse on the nindex pin, it then sets the ic code in status register 0 to "01" (abnormal termination), sets the ma bit in status register 1 to "1", and terminates the command. the following commands will generate an interrupt upon comple tion. they do not return any result bytes. it is highly recommended that control commands be follo wed by the sense interr upt status command. otherwise, valuable interrupt st atus information will be lost. recalibrate this command causes the read/write head within the fdc to retract to the track 0 position. the fdc clears the contents of the p cn counter and checks the status of the ntrk0 pin from the fdd. as long as the ntrk0 pin is low, the dir pin remains 0 and st ep pulses are issued. when the ntrk0 pin goes high, the se bit in status register 0 is set to "1" and t he command is terminated. if the ntr0 pin is still low after 79 step pulses have been issued, the fdc sets the se and the ec bits of status register 0 to "1" and terminates the command. disks capable of handling more than 80 tracks per side may require more than one recalibrate command to return t he head back to physical track 0. the recalibrate command does not have a result phase. the sense interrupt status command must be issued after the recalibrate command to effectively terminate it and to provide verification of the head position (pcn). during the command phase of the recalibra te operation, the fdc is in the busy state, but during the execution phase it is in a non-busy state. at this time, another recalibrate command may be issued, and in this manner parallel recalibrate operat ions may be done on up to four drives at once. upon power up, the software must issue a recalibrate command to properly initialize all dr ives and the controller. seek the read/write head within the drive is moved from track to track under the control of the seek command. the fdc compares the pcn, which is the current head position, with the ncn and performs the following operation if there is a difference: pcn < ncn: direction signal to drive set to "1" (step in) and issues step pulses. pcn > ncn: direction signal to drive set to "0" (step out) and issues step pulses. the rate at which step pulses are issued is cont rolled by srt (stepping rate time) in the specify command. after each step pulse is issued, ncn is compared against pcn, and when ncn = pcn the se bit in status register 0 is set to "1" and the command is terminated. duri ng the command phase of the seek or recalibrate operation, the fdc is in the bu sy state, but duri ng the execution phas e it is in the non-busy state. at this time, another seek or recalibrate command may be issued, and in this manner, parallel seek operations may be done on up to four drives at once. note that if implied seek is not enabled, the read and write commands should be preceded by: 1) seek command - step to the proper track 2) sense interrupt status co mmand - terminate the seek command
64 3) read id - verify head is on proper track 4) issue read/write command. the seek command does not have a resu lt phase. therefore, it is highly recommended that the sense interrupt status command is issued after the seek co mmand to terminate it and to provide verification of the head position (pcn). the h bit (head address) in st0 will always return to a "0". when exiting powerdown mode, the fdc clears the pcn value and the status informati on to zero. prior to issuing the powerdown command, it is hi ghly recommended that the user serv ice all pending interrupts through the sense interrupt status command. sense interrupt status an interrupt signal is generated by t he fdc for one of the following reasons: 1. upon entering the result phase of: a. read data command b. read a track command c. read id command d. read deleted data command e. write data command f. format a track command g. write deleted data command h. verify command 2. end of seek, relative seek, or recalibrate command 3. fdc requires a data transfer during th e execution phase in the non-dma mode the sense interrupt status command resets the interrupt signal and, via the ic code and se bit of status register 0, identifies the cause of the interrupt. table 25 - interrupt identification se ic interrupt due to 0 1 1 11 00 01 polling normal termination of seek or recalibrate command abnormal termination of seek or recalibrate command the seek, relative seek, and recalibrate commands hav e no result phase. t he sense interrupt status command must be issued immediately after these comm ands to terminate them and to provide verification of the head position (pcn). the h (head address) bit in st0 will always return a "0". if a sense interrupt status is not issued, the drive w ill continue to be busy and may affect the operation of the next command. sense drive status sense drive status obtains drive st atus information. it has not exec ution phase and goes directly to the result phase from the command phase. status register 3 contains the drive status information. specify the specify command sets the initial values for eac h of the three internal times. the hut (head unload time) defines the time from the end of t he execution phase of one of the read/write commands
65 to the head unload state. the srt (step rate time) defines the time interv al between adjacent step pulses. note that the spaci ng between the first and second step pulses may be shorter than the remaining step pulses. the hlt (head load time ) defines the time between when the head load signal goes high and the read/write operation starts. the values change with the data rate speed selection and are documented in table 26. the values are the same for mfm and fm. the choice of dma or non-dma operat ions is made by the nd bit. w hen this bit is "1", the non-dma mode is selected, and when nd is "0 ", the dma mode is selected. in dma mode, data transfers are signaled by the dma request cycles. non-dma mode us es the rqm bit and the in terrupt to signal data transfers. configure the configure command is issued to select the special f eatures of the fdc. a configure command need not be issued if the default values of the fdc meet the sy stem requirements. table 26 ? drive control delays (ms) hut srt 2m 1m 500k 300k 250k 2m 1m 500k 300k 250k 0 1 .. e f 64 4 .. 56 60 128 8 .. 112 120 256 16 .. 224 240 426 26.7 .. 373 400 512 32 .. 448 480 4 3.75 .. 0.5 0.25 8 7.5 .. 1 0.5 16 15 .. 2 1 26.7 25 .. 3.33 1.67 32 30 .. 4 2 hlt 2m 1m 500k 300k 250k 00 01 02 .. 7f 7f 64 0.5 1 .. 63 63.5 128 1 2 .. 126 127 256 2 4 .. 252 254 426 3.3 6.7 .. 420 423 512 4 8 . 504 508 configure default values: eis - no implied seeks efifo - fifo disabled poll - polling enabled fifothr - fifo threshold set to 1 byte pretrk - pre-compensation set to track 0 eis - enable implied seek. when set to "1", the fdc will perform a seek oper ation before executing a read or write command. defaults to no implied seek. efifo - a "1" disables the fifo (default). this means data transfers are asked for on a byte-by-byte basis. defaults to "1", fifo disabled. the threshold defaults to "1". poll - disable polling of the drives. defaults to "0", polling enabled. when enabled, a single interrupt is generated after a reset. no polling is performed while the drive head is loaded and the head unload delay has not expired.
66 fifothr - the fifo threshold in the execution phas e of read or write commands . this is programmable from 1 to 16 bytes. defaults to one byte. a "00" selects one byte; "0f" selects 16 bytes. pretrk - pre-compensation start track number. progra mmable from track 0 to 255. defaults to track 0. a "00" selects track 0; "ff" selects track 255. version the version command checks to see if the controller is an enhanced type or the older type (765a). a value of 90 h is returned as the result byte. relative seek the command is coded the same as for seek, except for the msb of the first byte and the dir bit. dir head step direction control rcn relative cylinder number that determines how m any tracks to step the head in or out from the current track number.
67 dir action 0 1 step head out step head in the relative seek command differs from the seek command in that it steps the head the absolute number of tracks specified in the command in stead of making a comparison against an internal register. the seek command is good for drives that support a maximum of 256 tracks. relative seeks cannot be overlapped with other relative seeks. only one relative s eek can be active at a time. relative seeks may be overlapped with seeks and recalibrates. bit 4 of stat us register 0 (ec) will be set if relative seek attempts to step outward beyond track 0. as an example, assume that a floppy drive has 300 useable tracks. the host needs to read track 300 and the head is on any track (0-255). if a seek command is i ssued, the head will stop at track 255. if a relative seek command is issued, the fdc will move the head the specified number of tr acks, regardless of the internal cylinder position register (but will increment the register). if the head was on track 40 (d), the maximum track that the fdc could posit ion the head on using relative seek will be 295 (d), the initial track + 255 (d). the maximum count t hat the head can be moved with a single relative seek command is 255 (d). the internal register, pcn, will ov erflow as the cylinder number crosse s track 255 and will contain 39 (d). the resulting pcn value is thus (rcn + pcn) mod 256. functionally, t he fdc starts counting from 0 again as the track number goes above 255 (d ). it is the user's responsib ility to compensate fdc functions (precompensation track number) when accessing tra cks greater than 255. the fdc does not keep track that it is working in an "extende d track area" (greater than 255). an y command issued will use the current pcn value except for the recalibrate command, which only looks for the track0 signal. recalibrate will return an error if the head is farther than 79 due to it s limitation of issuing a maximum of 80 step pulses. the user simply needs to issue a second recalib rate command. the seek command and implied seeks will function correctly within the 44 (d) track (299-255) area of the "extended track area". it is the user's responsibility not to issue a new track position that w ill exceed the maximum track that is present in the extended area. to return to the standard floppy range (0-255) of tra cks, a relative seek should be issued to cross the track 255 boundary. a relative seek can be used instead of the normal seek , but the host is required to calculate the difference between the current head location and the new (target) head location. this may require the host to issue a read id command to ensure that the head is physically on the track that software assumes it to be. different fdc commands will return different cylinder re sults which may be difficult to keep track of with software without the read id command. perpendicular mode the perpendicular mode command should be issued prio r to executing read/wri te/format commands that access a disk drive with perpendicular recording cap ability. with this command, the length of the gap2 field and vco enable timing can be altered to acco mmodate the unique requirement s of these drives. table 27 describes the effects of the wgate and g ap bits for the perpendicular mode command. upon a reset, the fdc will default to the conv entional mode (wgate = 0, gap = 0). selection of the 500 kbps and 1 m bps perpendicular modes is independent of the actual data rate selected in the data rate select register. the user must ensure that these two data rates remain consistent.
68 the gap2 and vco timing requirements for perpendicular re cording type drives are dictated by the design of the read/write head. in the design of this head, a pre-erase head precedes the norma l read/write head by a distance of 200 micr ometers. this works out to about 38 by tes at a 1 mbps recording density. whenever the write head is enabled by t he write gate signal, the pre-erase head is also activated at the same time. thus, when the write head is initially turned on, flux transitions reco rded on the media for the first 38 bytes will not be preconditioned with the pre-er ase head since it has not ye t been activated. to accommodate this head activation and deactivation time , the gap2 field is expanded to a length of 41 bytes. the format fields table illustrates the change in the gap2 field size for the perpendicular format. on the read back by the fdc, the cont roller must begin synchronization at the beginning of the sync field. for the conventional mode, the inte rnal pll vco is enabled (vcoen ) approximately 24 bytes from the start of the gap2 field. but, w hen the controller operates in the 1 mbps perpendicular mode (wgate = 1, gap = 1), vcoen goes active after 43 bytes to acco mmodate the increased gap2 field size. for both cases, and approximate two-byte cushion is maintai ned from the beginning of the sync field for the purposes of avoiding write splices in th e presence of motor speed variation. for the write data case, the fdc activates write gate at the beginning of the sync field under the conventional mode. the controller then writes a new sync field, data address mark, data field, and crc. with the pre-erase head of the perpendicular drive, t he write head must be activated in the gap2 field to insure a proper write of the new sync field. for the 1 mbps perpendicular mode (wgate = 1, gap = 1), 38 bytes will be written in the gap2 spac e. since the bit density is proportional to the data rate, 19 bytes will be written in the gap2 field for the 500 kbps perpendicular mode (wgate = 1, gap =0). it should be noted that none of the altera tions in gap2 size, vco timing, or write gate timing affect normal program flow. the information provided here is ju st for background purposes and is not needed for normal operation. once the perpendicula r mode command is invoked, fdc so ftware behavior from the user standpoint is unchanged. the perpendicular mode command is enhanced to allow specific drives to be designated perpendicular recording drives. this enhancement allows data tr ansfers between conventiona l and perpendicular drives without having to issue perpendicular mode commands between the accesses of t he different drive types, nor having to change write pr e-compensation values. when both gap and wgate bits of the perpendi cular mode command are both programmed to "0" (conventional mode), then d0, d1, d2, d3, and d4 can be programmed independently to "1" for that drive to be set automatically to perpendicular mode. in this mode the following set of conditions also apply: 1. the gap2 written to a perpendicular drive during a write operation will depend upon the programmed data rate. 2. the write pre-compensation given to a perpendicular mode drive will be 0ns. 3. for d0-d3 programmed to "0" for conventional m ode drives any data written will be at the currently programmed write pr e-compensation. note: bits d0-d3 can only be overwritten when ow is programmed as a "1".if either gap or wgate is a "1" then d0-d3 are ignored. software and hardware resets have the following effect on the perpendicular mode command: 1. "software" resets (via the dor or dsr registers) will only clear g ap and wgate bits to "0". d0-d3 are unaffected and retain their previous value. 2. "hardware" resets will clear all bits
69 (gap, wgate and d0-d3) to "0", i.e all conventional mode. table 27 ? effects of wgate and gap bits wgate gap mode length of gap2 format field portion of gap 2 written by write data operation 0 0 1 1 0 1 0 1 conventional perpendicular (500 kbps) reserved (conventional) perpendicular (1 mbps) 22 bytes 22 bytes 22 bytes 41 bytes 0 bytes 19 bytes 0 bytes 38 bytes lock in order to protect systems with long dma latencies against older application softw are that can disable the fifo the lock command has been added. this co mmand should only be used by the fdc routines, and application software should refrain from using it. if an application calls for the fi fo to be disabled then the configure command should be used. the lock command defines whether the efif o, fifothr, and pretrk parameters of the configure command can be reset by the dor and dsr registers. when the lock bit is set to logic "1" all subsequent "software resets by the dor and dsr registers will not change the previously set parameters to their default values. all "hardware" reset from the npci_reset pin will set the lock bit to logic "0" and return the efifo, fifothr, and pr etrk to their default values. a status byte is returned immediately after issuing a lock command. this byte reflects the value of the lock bit set by the command byte. enhanced dumpreg the dumpreg command is designed to support system run-time diagnostics and application software development and debug. to acco mmodate the lock command and the enhanced perpendicular mode command the eighth byte of the dumpreg command has been modified to contain the additional data from these two commands. compatibility the lpc47n227 was designed with software compatibility in mind. it is a fully backwards- compatible solution with the older generation 765a/b disk controlle rs. the fdc also implements on-board registers for compatibility with the ps/2, as well as pc/at and pc/xt, floppy disk controller subsystems. after a hardware reset of the fdc, all r egisters, functions and enhancements default to a pc/at, ps/2 or ps/2 model 30 compatible operating m ode, depending on how the ident and mfm bits are configured by the system bios. serial port (uart) the lpc47n227 incorporates two full function uarts. they are compatible with the ns16450, the 16450 ace registers and the ns16c550a. the uarts perfo rm serial-to-parallel conversion on received characters and parallel-to-serial conversion on transm it characters. the data rates are independently programmable from 460.8k baud down to 50 baud. the character options are progr ammable for 1 start; 1, 1.5 or 2 stop bits; even, odd, sticky or no parity; and prioritized interrupts. the uarts each contain a programmable baud rate generator that is capable of dividing the input clock or crystal by a number from 1
70 to 65535. the uarts are also capable of supporting the midi data rate. refe r to the configuration registers for information on disabling, power dow n and changing the base address of the uarts. the interrupt from a uart is enabled by programming out2 of that uart to a logic "1". out2 being a logic "0" disables that uart's interrupt. the second ua rt also supports irda 1.2 (4mbps), hp-sir, ask-ir and consumer ir infrared modes of operation. register description addressing of the accessible registers of the serial port is shown below. the base addresses of the serial ports are defined by the conf iguration registers (see conf iguration section). the se rial port registers are located at sequentially increasing addresses above t hese base addresses. the lpc47n227 contains two serial ports, each of which contain a register set as described below. table 28 - addressing the serial port dlab* a2 a1 a0 register name 0 0 0 0 receive buffer (read) 0 0 0 0 transmit buffer (write) 0 0 0 1 interrupt enable (read/write) x 0 1 0 interrupt identification (read) x 0 1 0 fifo control (write) x 0 1 1 line control (read/write) x 1 0 0 modem control (read/write) x 1 0 1 line stat us (read/write) x 1 1 0 modem stat us (read/write) x 1 1 1 scratchpad (read/write) 1 0 0 0 divisor lsb (read/write) 1 0 0 1 divisor msb (read/write *note: dlab is bit 7 of the line control register the following section describes t he operation of t he registers. receive buffer register (rb) address offset = 0h, dlab = 0, read only this register holds the received incoming data byte. bi t 0 is the least significant bit, which is transmitted and received first. received data is double buffered; th is uses an additional shift register to receive the serial data stream and convert it to a parallel 8 bit word which is transferred to the receive buffer register. the shift register is not accessible. transmit buffer register (tb) address offset = 0h, dlab = 0, write only this register contains the data byte to be transmi tted. the transmit buffer is double buffered, utilizing an additional shift register (not accessible) to convert the 8 bi t data word to a serial forma t. this shift register is loaded from the transmit buffer when the transmi ssion of the previous byte is complete. interrupt enable register (ier) address offset = 1h, dlab = 0, read/write the lower four bits of this register control the enables of the five in terrupt sources of the serial port interrupt. it is possible to totally di sable the interrupt system by resetting bits 0 through 3 of this register. similarly, setting the appropriate bits of this register to a high, selected interrupts can be enabled. disabling
71 the interrupt system inhibits the inte rrupt identification regist er and disables any serial port interrupt out of the lpc47n227. all other system functions operate in their normal ma nner, including the line status and modem status registers. the contents of the interrupt enable register are described below. bit 0 this bit enables the received data available interrupt (and timeout interrupts in the fifo mode) when set to logic "1". bit 1 this bit enables the transmitter holding register empty interrupt when set to logic "1". bit 2 this bit enables the received line stat us interrupt when set to logic "1". the error sources causing the interrupt are overrun, parity, framing and break. t he line status register must be read to determine the source. bit 3 this bit enables the modem status interrupt when set to logic "1". this is caused when one of the modem status register bits changes state. bits 4 through 7 these bits are always logic "0". fifo control register (fcr) address offset = 2h, dlab = x, write this is a write only register at the same location as the iir. this register is used to enable and clear the fifos, set the rcvr fifo trigger level. note: dma is not supported. the uart1 and uart2 fcr?s are shadowed in the uart1 fifo control shadow regi ster (cr15) and uart2 fifo control shadow register (cr16). see the configuration section for description on these registers.
72 bit 0 setting this bit to a logic "1" enables both the xmit and rcvr fifos. clearing this bit to a logic "0" disables both the xmit and rcvr fifos and clears a ll bytes from both fifos. when changing from fifo mode to non-fifo (16450) mode, data is automatically cl eared from the fifos. this bit must be a 1 when other bits in this register are written to or they will not be properly programmed. bit 1 setting this bit to a logic "1" clears all bytes in the rcv r fifo and resets its counter logic to 0. the shift register is not cleared. this bit is self-clearing. bit 2 setting this bit to a logic "1" clears all bytes in the xmit fifo and resets its counter logic to 0. the shift register is not cleared. this bit is self-clearing. bit 3 writing to this bit has no effect on the operation of the uart. dma modes are not supported in this chip. bit 4,5 reserved bit 6,7 these bits are used to set the trigge r level for the rcvr fifo interrupt. bit 7 bit 6 rcvr fifo trigger level (bytes) 0 0 1 0 1 4 1 0 8 1 1 14 interrupt identificati on register (iir) address offset = 2h, dlab = x, read by accessing this register, the host cpu can determine th e highest priority interrupt and its source. four levels of priority interrupt exist. t hey are in descending order of priority: 1. receiver line status (highest priority) 2. received data ready 3. transmitter holding register empty 4. modem status (lowest priority) information indicating that a prioritized interrupt is pendi ng and the source of that in terrupt is stored in the interrupt identification r egister (refer to interrupt control t able). when the cpu accesses the iir, the serial port freezes all interrupts and indicates the highes t priority pending interrupt to the cpu. during this cpu access, even if the serial port records new in terrupts, the current indi cation does not change until access is completed. the contents of the iir are described below.
73 bit 0 this bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt is pending. when bit 0 is a logic "0", an interrupt is pending and the contents of the iir may be used as a pointer to the appropriate internal se rvice routine. when bit 0 is a l ogic "1", no interrupt is pending. bits 1 and 2 these two bits of the iir are used to identify the hi ghest priority interrupt pending as indicated by the interrupt control table. bit 3 in non-fifo mode, this bit is a logic "0". in fifo mode this bit is set along with bit 2 when a timeout interrupt is pending. bits 4 and 5 these bits of the iir are always logic "0". bits 6 and 7 these two bits are set when the fifo control register bit 0 equals 1.
74 table 29 - interrupt control table fifo mode only interrupt identification register interrupt set and reset functions bit 3 bit 2 bit 1 bit 0 priority level interrupt type interrupt source interrupt reset control 0 0 0 1 - none none - 0 1 1 0 highest receiver line status overrun error, parity error, framing error or break interrupt reading the line status register 0 1 0 0 second received data available receiver data available read receiver buffer or the fifo drops below the trigger level. 1 1 0 0 second character timeout indication no characters have been removed from or input to the rcvr fifo during the last 4 char times and there is at least 1 char in it during this time reading the receiver buffer register 0 0 1 0 third transmitter holding register empty transmitter holding register empty reading the iir register (if source of interrupt) or writing the transmitter holding register 0 0 0 0 fourth modem status clear to send or data set ready or ring indicator or data carrier detect reading the modem status register
75 line control register (lcr) address offset = 3h, dlab = 0, read/write start lsb data 5-8 bits msb parity sto p figure 1 - serial data this register contains the format information of the serial line. the bit definitions are: bits 0 and 1 these two bits specify the number of bits in each transmitted or received serial character. the encoding of bits 0 and 1 is as follows: the start, stop and parity bits are not included in the word length. bit 1 bit 0 word length 0 0 1 1 0 1 0 1 5 bits 6 bits 7 bits 8 bits bit 2 this bit specifies the number of st op bits in each transmitted or rece ived serial character. the following table summarizes the information. bit 2 word length number of stop bits 0 -- 1 1 5 bits 1.5 1 6 bits 2 1 7 bits 2 1 8 bits 2 note: the receiver will ignore all stop bits beyond the first, regardless of the number used in transmitting. bit 3 parity enable bit. when bit 3 is a logic "1", a parit y bit is generated (transmit data) or checked (receive data) between the last data word bit and the first stop bit of the se rial data. (the parity bit is used to generate an even or odd number of 1s when the data word bits and the parity bit are summed). bit 4 even parity select bit. when bit 3 is a logic "1" and bit 4 is a logic "0", an odd number of logic "1"'s is transmitted or checked in the data word bits and the pari ty bit. when bit 3 is a logic "1" and bit 4 is a logic "1" an even number of bits is transmitted and checked.
76 bit 5 stick parity bit. when parity is enabled it is used in conj unction with bit 4 to select mark or space parity. when lcr bits 3, 4 and 5 are 1 the parity bit is transmi tted and checked as 0 (space parity). if bits 3 and 5 are 1 and bit 4 is a 0, then the parity bit is transmi tted and checked as 1 (mark parity). if bit 5 is 0 stick parity is disabled. bit 6 set break control bit. when bit 6 is a logic "1", the tr ansmit data output (txd) is forced to the spacing or logic "0" state and remains there (until reset by a low le vel bit 6) regardless of ot her transmitter activity. this feature enables the serial port to al ert a terminal in a communications system. bit 7 divisor latch access bit (dlab). it must be set high (logic "1") to access the div isor latches of the baud rate generator during read or write operations. it must be set low (l ogic "0") to access the receiver buffer register, the transmitter holding register , or the interrupt enable register. modem control register (mcr) address offset = 4h, dlab = x, read/write this 8 bit register controls the interface with the modem or data set (or device emulating a modem). the contents of the modem control r egister are described below. bit 0 this bit controls the data terminal ready (ndtr) output. when bit 0 is set to a logic "1", the ndtr output is forced to a logic "0". when bit 0 is a logic "0", the ndtr output is forced to a logic "1". bit 1 this bit controls the request to send (nrts) output. bit 1 affects the nrts out put in a manner identical to that described above for bit 0. bit 2 this bit controls the output 1 (out1) bit. this bit does not have an output pin and can only be read or written by the cpu. bit 3 output 2 (out2). this bit is used to enable an uart interrupt. when out2 is a logic "0", the serial port interrupt output is forced to a high im pedance state - disabled. when out2 is a logic "1", the serial port interrupt outputs are enabled. bit 4 this bit provides the loopback feature for diagnostic testing of the serial port. when bit 4 is set to logic "1", the following occur: 1. the txd is set to the marking state(logic "1"). 2. the receiver serial i nput (rxd) is disconnected. 3. the output of the transmitter shift register is "looped back" into the receiver shift register input. 4. all modem control inputs (ncts, ndsr, nri and ndcd) are disconnected. 5. the four modem contro l outputs (ndtr, nrts, out1 and out2) are internally connected to the four modem control inputs (ndsr, ncts, ri, dcd).
77 6. the modem control out put pins are forced inactive high. 7. data that is transmitted is immediately received. this feature allows the processor to verify the transmit and receive data paths of the serial port. in the diagnostic mode, the receiver and the transmitter inte rrupts are fully operational. the modem control interrupts are also operational but the interrupts' sources are now the lowe r four bits of the modem control register instead of the modem contro l inputs. the interrupts are still c ontrolled by the interrupt enable register. bits 5 through 7 these bits are permanently set to logic zero. line status register (lsr) address offset = 5h, dlab = x, read/write bit 0 data ready (dr). it is set to a logic "1" whenever a complete incoming character has been received and transferred into the receiver buffer register or the fif o. bit 0 is reset to a logic "0" by reading all of the data in the receive buffer register or the fifo. bit 1 overrun error (oe). bit 1 indicates that data in the receiver buffer register wa s not read before the next character was transferred into the r egister, thereby destroyin g the previous characte r. in fifo mode, an overrunn error will occur only when the fifo is full an d the next character has been completely received in the shift register, the character in the shift register is overwritten but not transferred to the fifo. the oe indicator is set to a logic "1" immediately upon dete ction of an overrun conditi on, and reset whenever the line status register is read. bit 2 parity error (pe). bit 2 indicates that the receiv ed data character does not hav e the correct even or odd parity, as selected by the even parity select bit. the pe is set to a logic "1" upon detection of a parity error and is reset to a logic "0" whenever the line status r egister is read. in the fifo mode this error is associated with the particular character in the fifo it applies to. this error is indicated when the associated character is at the top of the fifo. bit 3 framing error (fe). bit 3 indicates that the received c haracter did not have a valid stop bit. bit 3 is set to a logic "1" whenever the stop bit following the last data bi t or parity bit is detected as a zero bit (spacing level). the fe is reset to a logic "0" whenever the li ne status register is read. in the fifo mode this error is associated with the particular character in the fifo it applies to. this error is indicated when the associated character is at the top of th e fifo. the serial port will try to resynchronize after a framing error. to do this, it assumes that the framing error was due to the next start bit, so it samp les this 'start' bit twice and then takes in the 'data'.
78 bit 4 break interrupt (bi). bit 4 is set to a logic "1" whenever the received data input is held in the spacing state (logic "0") for longer than a full word transmission time (t hat is, the total time of the start bit + data bits + parity bits + stop bits). the bi is reset after the cpu reads the contents of the line status register. in the fifo mode this error is associated with the particular character in the fifo it applies to. this error is indicated when the associated characte r is at the top of the fifo. when break occurs only one zero character is loaded into the fifo. restarting after a br eak is received, requires the serial data (rxd) to be logic "1" for at least 1/2 bit time. note: bits 1 through 4 are the error conditions that pr oduce a receiver line status interrupt whenever any of the corresponding conditions are detec ted and the interrupt is enabled. bit 5 transmitter holding register empty (thre). bit 5 indica tes that the serial port is ready to accept a new character for transmission. in addition, this bit caus es the serial port to issue an interrupt when the transmitter holding register interrupt enable is set high. the thre bit is set to a logic "1" when a character is transferred from the transmitter holding regi ster into the transmitter shift register. the bit is reset to logic "0" whenever the cpu loads the transmitte r holding register. in the fifo mode this bit is set when the xmit fifo is empty, it is cleared when at least 1 byte is written to the xmit fifo. bit 5 is a read only bit. bit 6 transmitter empty (temt). bit 6 is set to a logic "1 " whenever the transmitter holding register (thr) and transmitter shift register (tsr) are both empty. it is reset to logic "0" whenever either the thr or tsr contains a data character. bit 6 is a read only bit. in the fifo mode this bit is set whenever the thr and tsr are both empty. bit 7 this bit is permanently set to logic "0" in the 450 mode. in the fifo mode, this bit is set to a logic "1" when there is at least one parity error, fram ing error or break indication in the fifo. this bit is cleared when the lsr is read if there are no s ubsequent errors in the fifo. modem status register (msr) address offset = 6h, dlab = x, read/write this 8 bit register provides the curr ent state of the control lines from the modem (or peripheral device). in addition to this current state information, four bits of the modem status regi ster (msr) provide change information. these bits are set to logic "1" whenever a control input from the mo dem changes state. they are reset to logic "0" whenever the modem status register is read. bit 0 delta clear to send (dcts). bit 0 indicates that t he ncts input to the chip has changed state since the last time the msr was read. bit 1 delta data set ready (ddsr). bit 1 indicates that the ndsr input has changed st ate since the last time the msr was read. bit 2
79 trailing edge of ring indicator (teri). bit 2 indicates that the nri input has changed from logic "0" to logic "1". bit 3 delta data carrier detect (ddcd). bit 3 indicates that the ndcd input to the chip has changed state. note: whenever bit 0, 1, 2, or 3 is set to a logic "1", a modem status interrupt is generated. bit 4 this bit is the complement of the clear to send (ncts) i nput. if bit 4 of the mcr is set to logic "1", this bit is equivalent to nrts in the mcr. bit 5 this bit is the complement of the data set ready (ndsr) input. if bit 4 of the mcr is set to logic "1", this bit is equivalent to dtr in the mcr. bit 6 this bit is the complement of the ring indicator (nri) input. if bit 4 of the m cr is set to logic "1", this bit is equivalent to out1 in the mcr. bit 7 this bit is the complement of the data carrier detect (ndcd) input. if bit 4 of the mcr is set to logi c "1", this bit is equivalent to out2 in the mcr. scratchpad register (scr) address offset =7h, dlab =x, read/write this 8 bit read/write register has no effect on the op eration of the serial port. it is intended as a scratchpad register to be used by the progra mmer to hold data temporarily. programmable baud rate generator (a nd divisor latches dlh, dll) the serial port contains a programm able baud rate generator that is ca pable of dividing the internal pll clock by any divisor from 1 to 65535. the internal pll clock is divided down to generate a 1.8462mhz frequency for baud rates less than 38.4k, a 1.8432m hz frequency for 115.2k, a 3.6864mhz frequency for 230.4k and a 7.3728mhz frequency for 460.8k. this output frequency of the baud rate generator is 16x the baud rate. two 8 bit latches store the divisor in 16 bit binary format. these divisor latches must be loaded during initialization in order to insure desire d operation of the baud rate generator. upon loading either of the divisor lat ches, a 16 bit baud counter is immediat ely loaded. this prevents long counts on initial load. if a 0 is loaded into the brg registers t he output divides the clock by the number 3. if a 1 is loaded the output is the inverse of the input oscillator. if a two is lo aded the output is a divide by 2 signal with a 50% duty cycle. if a 3 or gr eater is loaded the output is low for 2 bits and high for the remainder of the count. the input clock to the brg is a 1.8462 mhz clock. table 30 shows the baud rates possible. effect of the reset on register file the reset function table (table 31) details the effect of the reset input on each of the registers of the serial port. fifo interrupt mode operation
80 when the rcvr fifo and receiver interrupts are en abled (fcr bit 0 = "1", ier bit 0 = "1"), rcvr interrupts occur as follows: a. the receive data available interrupt will be issued when the fifo has reac hed its programmed trigger level; it is cleared as soon as the fifo drops below its programmed trigger level. b. the iir receive data available indication also occurs when the fifo trigger level is reached. it is cleared when the fifo drops below the trigger level. c. the receiver line status inte rrupt (iir=06h), has higher priori ty than the received data available (iir=04h) interrupt. d. the data ready bit (lsr bit 0) is set as soon as a character is transferred from the shift register to the rcvr fifo. it is reset when the fifo is empty. when rcvr fifo and receiver interrupts are enabled, rcvr fifo timeout interrupts occur as follows: a. a fifo timeout interrupt occurs if all the following conditions exist: at least one character is in the fifo. the most recent serial character received was longer than 4 continuous character times ago. (if 2 stop bits are programmed, the second one is included in this time delay). the most recent cpu read of the fifo was l onger than 4 continuous character times ago. this will cause a maximum character received to inte rrupt issued delay of 160 msec at 300 baud with a 12 bit character. b. character times are calculated by using the rclk input for a clock signal (this makes the delay proportional to the baudrate). c. when a timeout interrupt has occurred it is cleared and the timer reset when the cpu reads one character from the rcvr fifo. d. when a timeout interrupt has not o ccurred the timeout timer is reset after a new character is received or after the cpu reads the rcvr fifo. when the xmit fifo and transmitter interrupts ar e enabled (fcr bit 0 = "1", ier bit 1 = "1"), xmit interrupts occur as follows: a. the transmitter holding register interrupt (02h) occu rs when the xmit fifo is empty; it is cleared as soon as the transmitter holding register is written to (1 of 16 characters may be written to the xmit fifo while servicing this interrupt) or the iir is read. b. the transmitter fifo empty indications will be delay ed 1 character time minus the last stop bit time whenever the following occurs: thre=1 and there hav e not been at least two bytes at the same time in the transmitter fifo since the last thre=1. t he transmitter interrupt after changing fcr0 will be immediate, if it is enabled. character timeout and rcvr fifo trigger level interrupt s have the same priority as the current received data available interrupt; xmit fifo empty has the same priority as the current transmitter holding register empty interrupt. fifo polled mode opertion with fcr bit 0 = "1" resetting ier bits 0, 1, 2 or 3 or all to zero puts the uart in the fifo polled mode of operation. since the rcvr and xmi tter are controlled separately, eit her one or both can be in the polled mode of operation. in this mode, the user's program will check rcvr and xmitter status via the lsr. lsr definitions for the fifo polled mode are as follows: bit 0=1 as long as there is one byte in the rcvr fifo.
81 bits 1 to 4 specify which error(s) have occurred. char acter error status is handled the same way as when in the interrupt mode, the iir is not affected since eir bit 2=0. bit 5 indicates when the xmit fifo is empty. bit 6 indicates that both the xmit fifo and shift register are empty. bit 7 indicates whether there are any errors in the rcvr fifo. there is no trigger level reached or timeout conditi on indicated in the fifo polled mode, however, the rcvr and xmit fifos are still fully capable of holding characters. table 30 ? baud rates desired baud rate divisor used to generate 16x clock percent error difference between desired and actual 1 high speed bit 2 50 2304 0.001 x 75 1536 - x 110 1047 - x 134.5 857 0.004 x 150 768 - x 300 384 - x 600 192 - x 1200 96 - x 1800 64 - x 2000 58 0.005 x 2400 48 - x 3600 32 - x 4800 24 - x 7200 16 - x 9600 12 - x 19200 6 - x 38400 3 0.030 x 57600 2 0.16 x 115200 1 0.16 x 230400 32770 0.16 1 460800 32769 0.16 1 note 1 : the percentage error for all baud rates, exc ept where indicated otherwise, is 0.2%. note 2 : the high speed bit is located in the device configuration space.
82 table 31 - reset function table register/signal reset control reset state interrupt enable register reset all bits low interrupt identification reg. reset bit 0 is high; bits 1 - 7 low fifo control reset all bits low line control reg. reset all bits low modem control reg. reset all bits low line status reg. reset all bits low except 5, 6 high modem status reg. reset bits 0 - 3 low; bits 4 - 7 input txd1, txd2 reset high intrpt (rcvr errs) reset/read lsr low intrpt (rcvr data ready) reset/read rbr low intrpt (thre) reset/readiir/write thr low out2b reset high rtsb reset high dtrb reset high out1b reset high rcvr fifo reset/ fcr1*fcr0/_fcr0 all bits low xmit fifo reset/ fcr1*fcr0/_fcr0 all bits low
83 table 32 ? register summary for an individual uart channel register address* register name register symbol bit 0 bit 1 addr = 0 dlab = 0 receive buffer register (read only) rbr data bit 0 (note 1) data bit 1 addr = 0 dlab = 0 transmitter holding register (write only) thr data bit 0 data bit 1 addr = 1 dlab = 0 interrupt enable register ier enable received data available interrupt (erdai) enable transmitter holding register empty interrupt (ethrei) addr = 2 interrupt ident. register (read only) iir "0" if interrupt pending interrupt id bit addr = 2 fifo control register (write only) fcr (note 7) fifo enable rcvr fifo reset addr = 3 line control register lcr word length select bit 0 (wls0) word length select bit 1 (wls1) addr = 4 modem control register mcr data terminal ready (dtr) request to send (rts) addr = 5 line status register lsr data ready (dr) overrun error (oe) addr = 6 modem status regist er msr delta clear to send (dcts) delta data set ready (ddsr) addr = 7 scratch register (note 4) scr bit 0 bit 1 addr = 0 dlab = 1 divisor latch (ls) ddl bit 0 bit 1 addr = 1 dlab = 1 divisor latch (ms) dlm bit 8 bit 9 *dlab is bit 7 of the line control register (addr = 3). note 1: bit 0 is the least significant bit. it is the first bit serially transmitted or received. note 2: when operating in the xt mode, this bit will be set any time that the tran smitter shift register is empty.
84 table 32 - register summary for an individual uart channel (continued) bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 data bit 2 data bit 3 data bit 4 data bit 5 data bit 6 data bit 7 data bit 2 data bit 3 data bit 4 data bit 5 data bit 6 data bit 7 enable receiver line status interrupt (elsi) enable modem status interrupt (emsi) 0 0 0 0 interrupt id bit interrupt id bit (note 5) 0 0 fifos enabled (note 5) fifos enabled (note 5) xmit fifo reset dma mode select (note 6) reserved reserved rcvr trigger lsb rcvr trigger msb number of stop bits (stb) parity enable (pen) even parity select (eps) stick parity set break divisor latch access bit (dlab) out1 (note 3) out2 (note 3) loop 0 0 0 parity error (pe) framing error (fe) break interrupt (bi) transmitter holding register (thre) transmitter empty (temt) (note 2) error in rcvr fifo (note 5) trailing edge ring indicator (teri) delta data carrier detect (ddcd) clear to send (cts) data set ready (dsr) ring indicator (ri) data carrier detect (dcd) bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 10 bit 11 bit 12 bit 13 bit 14 bit 15 note 3: this bit no longer has a pin associated with it. note 4: when operating in the xt mode , this register is not available. note 5: these bits are always zero in the non-fifo mode. note 6: writing a one to this bit has no effe ct. dma modes are not supported in this chip. note 7: the uart1 and uart2 fcr?s are shadowed in the uart1 fifo cont rol shadow register (cr15) and uart2 fifo control shadow register (cr16).
85 notes on serial port operation fifo mode operation general the rcvr fifo will hold up to 16 bytes regard less of which trigger level is selected. tx and rx fifo operation the tx portion of the uart transmits data through txd as soon as the cpu loads a byte into the tx fifo. the uart will prevent loads to the tx fi fo if it currently holds 16 characters. loading to the tx fifo will again be enabled as soon as t he next character is transferred to the tx shift register. these capabilities account for the largel y autonomous operation of the tx. the uart starts the above operations typically with a tx interrupt. the chip issues a tx interrupt whenever the tx fifo is empty and the tx interrupt is enabled, except in the fo llowing instance. assume that the tx fifo is empty and the cp u starts to load it. when the first byte enters the fifo the tx fifo empty interrupt will transition from active to inacti ve. depending on the execut ion speed of the service routine software, the uart may be able to transfer this byte from the fifo to t he shift register before the cpu loads another byte. if this happens, the tx fifo will be empty again and typically the uart's interrupt line would transition to the ac tive state. this could cause a syst em with an interrupt control unit to record a tx fifo empty condition, even though t he cpu is currently servicing that interrupt. therefore, after the first byte has been lo aded into the fifo the uart will wait one serial character transmission time before issuing a new tx fifo empty interrupt. this one character tx interrupt delay will remain active until at least two bytes have the tx fifo empties afte r this condition, the tx been loaded into the fifo, concurrently. when interrupt will be activated without a one character delay. rx support functions and operation ar e quite different from those descr ibed for the transmitter. the rx fifo receives data until the number of bytes in the fifo equals the sele cted interrupt trigger level. at that time if rx interrupts are enabled, t he uart will issue an interrupt to the cpu. the rx fifo will continue to store bytes until it holds 16 of them. it will not accept any more data when it is full. any more data entering the rx shift register will set the overrun error fl ag. normally, the fifo depth and the programmable trigger levels will give the cpu ample time to em pty the rx fifo before an overrun occurs. one side-effect of having a rx fifo is that the selected interrupt tri gger level may be above the data level in the fifo. this could occur when data at the end of the blo ck contains fewer bytes than the trigger level. no interrupt would be issued to the cpu an d the data would remain in the uart. to prevent the software from having to check for this situation the chip incorporates a timeout interrupt. the timeout interrupt is activated w hen there is a least one byte in the rx fifo, and neither the cpu nor the rx shift register has accessed th e rx fifo within 4 character times of the last byte. the timeout interrupt is cleared or reset when the cpu reads the rx fifo or another character enters it. these fifo related features allo w optimization of cpu/uart trans actions and are especially useful given the higher baud rate capability (256 kbaud).
86 infrared interface the lpc47n227 infrared interface provides a two-wa y wireless communications port using infrared as the transmission medium. several infrared prot ocols have been provided in this implementation including irda v1.2 (sir/fir), askir, and consumer ir (figure 2). for more information consult the smsc infrared communication cont roller (ircc) specification. the irda v1.0 (sir) and askir formats are driven by the ace registers found in uart2. the uart2 registers are described in ?serial port (uart)? sect ion. the base address for uart2 is programmed in cr25, the uart2 base address register (see secti on cr25 subsection in the configuration seciton). the irda v1.2 (fir) and consumer ir formats are dr iven by the sce registers. descriptions of these registers can be found in the smsc infrared communications controlle r specification. the base address for the sce registers is programmed in cr2b, the sce base address register (see cr28 subsection in the conf iguration section). irda sir/fir and askir irda sir (v1.0) specifies asynchronous serial co mmunication at baud rates up to 115.2kbps. each byte is sent serially lsb first beginning with a zero value start bit. a zero is signaled by sending a single infrared pulse at the beginning of the serial bit ti me. a one is signaled by the absence of an infrared pulse during the bit time. please refer to ?timing diagrams? section for the parameters of these pulses and the irda waveforms. irda fir (v1.2) includes irda v1.0 sir and additiona lly specifies synchronous serial communications at data rates up to 4mbps. data is transferred lsb first in packets that can be up to 2048 bits in length. irda v1.2 includes .576mbps and 1.152mbps data rates usi ng an encoding scheme that is sim ilar to sir. the 4mbps data rate uses a pulse position modulation (ppm) technique. the askir infrared allows asynchronous serial co mmunication at baud rates up to 19.2kbps. each byte is sent serially lsb first beginning with a ze ro value start bit. a zero is signaled by sending a 500khz carrier waveform for the duration of the seri al bit time. a one is signaled by the absence of carrier during the bit time. refer to ?timing diagrams? section for t he parameters of the askir waveforms. consumer ir the lpc47n227 consumer ir interface is a gener al-purpose amplitude shi ft keyed encoder/decoder with programmable carrier and bit-cell rates that can emulate many popular tv remote encoding formats; including, 38khz ppm, pwm and rc-5. t he carrier frequency is progr ammable from 1.6mhz to 6.25khz. the bit-cell rate range is 100khz to 390hz.
87 hardware interface the lpc47n227 ir hardware interface is shown in figure 2. this interface supports two types of external fir transceiver modules. one uses a mode pin (ir mode) to program the data rate, while t he other has a second rx data pin (irrx3). the lpc47n227 uses pin 63 for these functions. pin 63 has ir mode and irrx3 as its first and second alternate function, respectively . these functions are selected th rough cr29 as shown in table 33. table 33 - fir transceiver module-type select hp mode 1 function 0 ir mode 1 irrx3 note 1 hpmode is cr29, bit 4 (see cr 29 subsection in the configurat ion section). refer to the infrared interface block diagram on the following page for hpmode implementation. the fast bit is used to select between the si r mode and fir mode receiver, regardless of the transceiver type. if fast = 1, the fir mode receiver is selected; if fast = 0, the sir mode receiver is selected (table 34). table 34 ? ir rx data pin selection control signals inputs fast hpmode rx1 rx2 0 x rx1=rxd2 rx2=irrx2 x 0 rx1=rxd2 rx2=irrx2 1 1 rx1=ir mode/irrx 3 rx2=ir mode/irrx3
88 ir half duplex turnaround delay time if the half duplex option is chosen there is an ir half duplex time- out that constrai ns ircc direction mode changes. this time-out starts as each bi t is transferred and prevent s direction mode changes until the time-out expires. the ti mer is restarted whenever new data arrives in the current direction mode. for example, if data is loaded into the transmit buffer while a character is being received, the transmission will not start until the last bit has been received and the time-out expires. if the start bit of another character is received during this time-out, t he timer is restarted after the new character is received. the half duplex time-out is programmable from 0 to 25.5ms in 100 s increments (see section (see subsection cr2d in the configuration section). figure 2 ? infrared interface block diagram ir transmit pins the txd2 and irtx2 pins default to output, low on vcc por and hard reset. these pins are not powered by vtr. these pins function as described below. following a vcc por, the txd2 and irtx2 pins will be output and low. they will remain low until one of the following conditions are met. irtx2 pin (cr0a bits [7:6]=01): ? this pin will remain low following a vcc por until serial port 2 is enabled by setting the uart2 power down bit (cr02, bit 7), at which time the pin will reflect the state of the ir transmit output of the ircc block (if ir is enabled through the ir option register for serial port 2). ircc block raw tv ask irda fir com out mux com ir aux tx1 rx1 tx2 rx2 tx3 rx3 1 2 ir mode fast hpmode 0 1 1 0 g.p. data fast bit rxd2 irtx2 irrx2 txd2 ir mode /irrx3
89 txd2 pin (cr0a bits [7:6]=00): 1. this pin will remain low following a vcc por until serial port 2 is enabled by setting the uart2 power down bit (cr02, bit 7), at which time the pi n will reflect the state of the transmit output of serial port 2 (if com is enabled through cr0c register for serial port 2). 2. this pin will remain low following a vcc por until serial port 2 is enabled by setting the uart2 power down bit (cr02, bit 7), at which time the pin will reflect the state of the ir transmit output of the ircc block (if ir is enabled through t he cr0c register for serial port 2). the irtx2 and txd2 pins will be driven low whenever serial port 2 is disabled (uart2 power down bit is cleared). note that bits[7,6] of cr0a can be used to override th is functionality of drivi ng the irtx2 and txd2 pins low when uart2 is powered down. if these bits are set to ?11?, then the irtx (txd2) and irtx2 pins are high-z.
90 parallel port the lpc47n227 incorporates an ibm xt/at compatible parallel port. th is supports the optional ps/2 type bi-directional parallel port (spp), the enhanced pa rallel port (epp) and the extended capabilities port (ecp) parallel port modes. refer to the configurati on registers for information on disabling, power down, changing the base address of the parallel por t, and selecting the mode of operation. the lpc47n227 also provides a mode for support of the floppy disk controller on the parallel port. the parallel port also incorporates smsc's chiprote ct circuitry, which prevents possible damage to the parallel port due to printer power-up. the functionality of the parallel port is achieved through the use of ei ght addressable ports, with their associated registers and control gating. the control and data port are read/wr ite by the cpu, the status port is read/write in the epp mode. the address map of the parallel port is shown below data port base address + 00h status port base address + 01h control port base address + 02h epp addr port base address + 03h epp data port 0 base address + 04h epp data port 1 base address + 05h epp data port 2 base address + 06h epp data port 3 base address + 07h the bit map of these registers is: d0 d1 d2 d3 d4 d5 d6 d7 note data port pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 1 status port tmout 0 0 nerr slct pe nack nbusy 1 control port strobe autofd ninit slc irqe pcd 0 0 1 epp addr port pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 2 epp data port 0 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 2 epp data port 1 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 2 epp data port 2 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 2 epp data port 3 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 2 note 1: these registers are available in all modes. note 2: these registers are only available in epp mode.
91 table 35 - parallel port connector host connector pin number standard epp ecp 1 83 nstrobe nwrite nstrobe 2-9 68-75 pd<0:7> pdata<0:7> pdata<0:7> 10 80 nack intr nack 11 79 busy nwait busy, periphack(3) 12 78 pe (user defined) perror, nackreverse(3) 13 77 slct (user defined) select 14 82 nalf ndatastb nautofd, hostack(3) 15 81 nerror (user defined) nfault(1) nperiphrequest(3) 16 66 ninit nreset ninit(1) nreverserqst(3) 17 67 nslctin naddrstrb nselectin(1,3) (1) = compatible mode (3) = high speed mode note: for the cable interconnection required for ecp support and the slave connector pin numbers, refer to the ieee 1284 extended capabilit ies port protocol and isa standard , rev. 1.14, july 14, 1993. this document is available from microsoft. ibm xt/at compatible, bi-directional and epp modes data port address offset = 00h the data port is located at an offset of '00h' fr om the base address. the dat a register is cleared at initialization by reset. during a write operation, the data register latches the contents of the internal data bus. the contents of this regi ster are buffered (non inverting) an d output onto the pd0 - pd7 ports. during a read operation in spp mode, pd0 - pd7 port s are buffered (not latc hed) and output to the host cpu. status port address offset = 01h the status port is located at an offs et of '01h' from the base address. the contents of th is register are latched for the duration of a read cycle. the bits of the status port are defined as follows: bit 0 tmout - time out this bit is valid in epp mode only and indicates that a 10 usec time out has occurred on the epp bus. a logic zero means that no time out error has occurr ed; a logic 1 means that a time out error has been detected. the means of clearing the timeout bit is contro lled by the timeout_select bit as follows. the timeout_select bit is located at bit 2 of cr21.
92 ? if the timeout_select bit is cleared (?0?), the timeout bit is cleared on the trailing edge of the read of the epp status register (default) ? if the timeout_select bit is set (?1?), the ti meout bit is cleared on a write of ?1? to the timeout bit. the timeout bit is cleared on pci_reset regardl ess of the state of the timeout_select bit. bits 1, 2 - are not implemented as register bits, during a read of the printer status register these bits are a low level. bit 3 nerr - nerror the level on the nerror input is read by the cpu as bi t 3 of the printer status register. a logic 0 means an error has been detected; a logic 1 means no error has been detected. bit 4 slct - printer selected status the level on the slct input is read by the cpu as bit 4 of the printer status regi ster. a logic 1 means the printer is on line; a logic 0 means it is not selected. bit 5 pe - paper end the level on the pe input is read by the cpu as bit 5 of the printer status register. a logic 1 indicates a paper end; a logic 0 indicates the presence of paper. bit 6 nack - nacknowledge the level on the nack input is read by the cpu as bit 6 of the printer status register. a logic 0 means that the printer has received a char acter and can now accept another. a logic 1 means that it is still processing the last character or has not received the data. bit 7 nbusy - nbusy the complement of the level on the busy input is read by the cpu as bit 7 of the printer status register. a logic 0 in this bit means that the printer is busy and cannot accept a new characte r. a logic 1 means that it is ready to accept the next character. control port address offset = 02h the control port is located at an offs et of '02h' from the base address. the control register is initialized by the reset input, bits 0 to 5 only being affected; bits 6 and 7 are hard wired low. bit 0 strobe - strobe this bit is inverted and out put onto the nstrobe output. bit 1 autofd - autofeed this bit is inverted and output ont o the nautofd output. a logic 1 c auses the printer to generate a line feed after each line is printed. a logic 0 means no autofeed.
93 bit 2 ninit - ninitiate output this bit is output onto the ni nit output without inversion. bit 3 slctin - printer select input this bit is inverted and output onto t he nslctin output. a logic 1 on this bit selects the printer; a logic 0 means the printer is not selected. bit 4 irqe - interrupt request enable the interrupt request enable bit when set to a high leve l may be used to enable interrupt requests from the parallel port to the cpu. an interrupt request is generated on the irq port by a positive going nack input. when the irqe bit is programmed low the irq is disabled. bit 5 pcd - parallel control direction parallel control direction is not valid in printer mode. in printer mode, the direction is always out regardless of the state of this bit. in bi-directional, epp or ecp mode, a logic 0 means that t he printer port is in output mode (write); a logic 1 means that t he printer port is in input mode (read). bits 6 and 7 during a read are a lo w level, and cannot be written. epp address port address offset = 03h the epp address port is located at an o ffset of '03h' from the base address. the address register is cleared at initialization by reset. during a write operat ion, the contents of t he internal data bus db0- db7 are buffered (non inverting) and output onto the pd0 - pd7 ports. an lpc i/o write cycle causes an epp address write cycle to be performed, during which the data is latched for the duration of the epp write cycle. during a read operation, pd0 - pd7 ports are read. an lpc i/o read cycle causes an epp address read cycle to be performed and the data output to the host cp u, the deassertion of addrstb latches the pdata for the dur ation of the read cycle. this register is only available in epp mode. epp data port 0 address offset = 04h the epp data port 0 is located at an offset of '04h' from the base address. the data register is cleared at initialization by reset. during a write operation, th e contents of the inter nal data bus db0-db7 are buffered (non inverting) and output onto the pd0 - pd7 ports. an lpc i/o write cycle causes an epp data write cycle to be performed, during which t he data is latched for the duration of the epp write cycle. during a read operation, pd0 - pd7 ports ar e read. an lpc i/o read cycle causes an epp read cycle to be performed and the data output to the host cpu, the deassertion of da tastb latches the pdata for the duration of the read cycle. this register is only available in epp mode. epp data port 1 address offset = 05h the epp data port 1 is located at an offset of '05h ' from the base address. refer to epp data port 0 for a description of operation. this r egister is only available in epp mode. epp data port 2
94 address offset = 06h the epp data port 2 is located at an offset of '06h' from the base addr ess. refer to epp data port 0 for a description of operation. this r egister is only available in epp mode. epp data port 3 address offset = 07h the epp data port 3 is located at an offset of '07h' from the base addr ess. refer to epp data port 0 for a description of operation. this r egister is only available in epp mode. epp 1.9 operation when the epp mode is selected in th e configuration regist er, the standard and bi-d irectional modes are also available. if no epp read, write or address cycle is currently executing, then the pdx bus is in the standard or bi-directional mode, and all output signals (strobe, autofd, init) are as set by the spp control port and direction is contro lled by pcd of the control port. in epp mode, the system timing is closely coupled to the epp timing. for this reason, a watchdog timer is required to prevent system lockup. the timer indica tes if more than 10usec have elapsed from the start of the epp cycle to nwait being deasserted (after command). if a time-out occurs, the current epp cycle is aborted and the time-out condition is indicated in status bit 0. during an epp cycle, if strobe is active, it overrides the epp write signal forcing the pdx bus to always be in a write mode and the nwrite signal to always be asserted. software constraints before an epp cycle is executed, the software must ensur e that the control register bit pcd is a logic "0" (i.e., a 04h or 05h should be written to the contro l port). if the user leaves pcd as a logic "1", and attempts to perform an epp write, the chip is unable to perform the write (because pcd is a logic "1") and will appear to perform an epp read on the parallel bus, no error is indicated. epp 1.9 write the timing for a write operation (address or data) is shown in timing diagram epp write data or address cycle. the chip inserts wait stat es into the lpc i/o write cycle until it has been determine d that the write cycle can complete. the write cycle can complete under the following circumstances: 1. if the epp bus is not ready (nwait is active low) when ndatastb or naddrstb goes active then the write can complete when nwait goes inactive high. 2. if the epp bus is ready (nwait is inactive high) t hen the chip must wait for it to go active low before changing the state of ndatastb, nw rite or naddrstb. the write can complete once nwait is determined inactive. write sequence of operation 1. the host initiates an i/o write cy cle to the selected epp register. 2. if wait is not asserted, the chip must wait until wait is asserted. 3. the chip places address or data on pd ata bus, clears pdir, and asserts nwrite. 4. chip asserts ndatastb or naddrstrb indicating that pdata bus contains valid information, and the write signal is valid. 5. peripheral deasserts nwait, indicating that any setup requirements have been satisfied and the chip may begin the termination phase of the cycle.
95 6. a) the chip deasserts ndatastb or naddrstrb, this marks the beginning of the termination phase. if it has not already done so, the peri pheral should latch the information byte now. b) the chip latches the data from the internal dat a bus for the pdata bus and drives the sync that indicates that no more wait states are required fo llowed by the tar to complete the write cycle. 7. peripheral asserts nwait, indicating to the hos t that any hold time requirements have been satisfied and acknowledging the termination of the cycle. 8. chip may modify nwrite and npdata in preparation for the next cycle. epp 1.9 read the timing for a read operation (data) is shown in ti ming diagram epp read data cycle. the chip inserts wait states into the lpc i/o read cy cle until it has been dete rmined that the read cycle can complete. the read cycle can complete under the following circumstances: 1 if the epp bus is not ready (nwait is active low) when ndatastb goes active then the read can complete when nwait goes inactive high. 2. if the epp bus is ready (nwait is inactive high) t hen the chip must wait for it to go active low before changing the state of write or before ndatastb g oes active. the read can complete once nwait is determined inactive. read sequence of operation 1. the host initiates an i/o read cycle to the selected epp register. 2. if wait is not asserted, the chip must wait until wait is asserted. 3. the chip tri-states the pd ata bus and deasserts nwrite. 4. chip asserts ndatastb or naddrstrb indicating t hat pdata bus is tri-stated, pdir is set and the nwrite signal is valid. 5. peripheral drives pdata bus valid. 6. peripheral deasserts nwait, indicating that pdat a is valid and the chip may begin the termination phase of the cycle. 7. a) the chip latches the data from the pdata bus for the internal data bus and deasserts ndatastb or naddrstrb. this marks the beginning of the termination phase. b) the chip drives the sync that indicates that no more wait states are required and drives valid data onto the lad[3:0] signals, followed by t he tar to complete the read cycle. 8. peripheral tri-states t he pdata bus and asserts nwait, indicating to the host that the pdata bus is tri- stated. 9. chip may modify nwrite, pdir and np data in preparation for the next cycle. epp 1.7 operation when the epp 1.7 mode is selected in the configuration register, the standard and bi-directional modes are also available. if no epp read, write or address cycle is currently executing, then the pdx bus is in the standard or bi-directional mode, and all output signals (strobe, autofd, init) are as set by the spp control port and direction is contro lled by pcd of the control port. in epp mode, the system timing is closely coupled to the epp timing. for this reason, a watchdog timer is required to prevent system lockup. the timer indica tes if more than 10usec have elapsed from the start of the epp cycle to the end of the cycle. if a time-out occurs, the current epp cycle is aborted and the time- out condition is indicated in status bit 0. software constraints
96 before an epp cycle is executed, the software must ensure that the control register bits d0, d1 and d3 are set to zero. also, bi t d5 (pcd) is a logic "0" for an epp write or a logic "1" for and epp read. epp 1.7 write the timing for a write operation (address or data) is shown in timing diagram epp 1.7 write data or address cycle. the chip inserts wait states into the i/o write cycle when nwait is active low during the epp cycle. this can be used to extend the cycle ti me. the write cycle can complete when nwait is inactive high. write sequence of operation 1. the host sets pdir bit in the control regist er to a logic "0". this asserts nwrite. 2. the host initiates an i/o write cycle to the selected epp register. 3. the chip places address or data on pdata bus. 4. chip asserts ndatastb or naddrstrb indicating that pdata bus contains valid information, and the write signal is valid. 5. if nwait is asserted, the chip inserts wait states into i/o write cycle until the peripheral deasserts nwait or a time-out occurs. 6. the chip drives the final sync, deasserts ndatastb or naddrstrb and la tches the data from the internal data bus for the pdata bus. 7. chip may modify nwrite, pdir and npda ta in preparation of the next cycle. epp 1.7 read the timing for a read operation (data) is shown in timing diagram epp 1.7 read data cycle. the chip inserts wait states into the i/o r ead cycle when nwait is active low during the epp cycle. this can be used to extend the cycle time. the read cycle can complete when nwait is inactive high. read sequence of operation 1. the host sets pdir bit in the control register to a logic "1". this deassert s nwrite and tri-states the pdata bus. 2. the host initiates an i/o read cycle to the selected epp register. 3. chip asserts ndatastb or naddrstrb indicating t hat pdata bus is tri-stat ed, pdir is set and the nwrite signal is valid. 4. if nwait is asserted, the chip inserts wait states into the i/o re ad cycle until the peripheral deasserts nwait or a time-out occurs. 5. the peripheral drives pdata bus valid. 6. the peripheral deasserts nwait, indicating that pdata is valid and the chip may begin the termination phase of the cycle. 7. the chip drives the final sync and deasserts ndatastb or naddrstrb. 8. peripheral tri-st ates the pdata bus. 9. chip may modify nwrite, pdir and npda ta in preparation of the next cycle.
97 table 36 - epp pin descriptions epp signal epp name type epp description nwrite nwrite o this signal is active low. it denotes a write operation. pd<0:7> address/data i/o bi-directional epp byte wide address and data bus. intr interrupt i this signal is active high and positive edge triggered. (pass through with no inversion, same as spp). wait nwait i this signal is active low. it is driven inactive as a positive acknowledgement from the device that the transfer of data is completed. it is driven active as an indication that the device is ready for the next transfer. datastb ndata strobe o this signal is active low. it is used to denote data read or write operation. reset nreset o this signal is active low. when driven active, the epp device is reset to its initial operational mode. addrstb naddress strobe o this signal is active low. it is used to denote address read or write operation. pe paper end i same as spp mode. slct printer selected status i same as spp mode. nerr error i same as spp mode. note 1: spp and epp can use 1 common register. note 2: nwrite is the only epp output that can be over-ridden by spp control port during an epp cycle. for correct epp read cycles, pcd is required to be a low. extended capabilities parallel port ecp provides a number of advantag es, some of which are listed belo w. the individual features are explained in greater detail in t he remainder of this section. high performance half-duplex forward and reverse channel interlocked handshake, for fast reliable transfer optional single byte rle compression for improved throughput (64:1) channel addressing for low-cost peripherals maintains link and data layer separation permits the use of active output drivers permits the use of adaptive signal timing p eer-to-peer capability. vocabulary the following terms are used in this document: assert: when a signal asserts it transit ions to a "true" state, when a si gnal deasserts it transitions to a "false" state. forward: host to pe ripheral communication. reverse: peripheral to host communication pword: a port word; equal in size to the width of th e lpc interface. for this implementation, pword is always 8 bits. 1 a high level. 0 a low level. these terms may be considered synonymous: periphclk, nack hostack, nautofd
98 periphack, busy nperiphrequest, nfault nreverserequest, ninit nackreverse, perror xflag, select ecpmode, nselectln hostclk, nstrobe reference document: ieee 1284 extended capabilit ies port protocol and isa interface standard , rev 1.14, july 14, 1993. this document is available from microsoft. the bit map of the extended parallel port registers is: d7 d6 d5 d4 d3 d2 d1 d0 note data pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 ecpafifo addr/rle address or rle field 2 dsr nbusy nack perror select nfault 0 0 0 1 dcr 0 0 direction ackinten selecti n ninit autofd strobe 1 cfifo parallel port data fifo 2 ecpdfifo ecp data fifo 2 tfifo test fifo 2 cnfga 0 0 0 1 0 0 0 0 cnfgb compress intrvalue parallel port irq parallel port dma ecr mode nerrintre n dmaen serviceintr full empty note 1: these registers are available in all modes. note 2: all fifos use one common 16 byte fifo. note 3: the ecp parallel port config reg b reflects the irq and dma channel selected by the configuration registers. ecp implementation standard this specification describes the standard interface to the extended ca pabilities port (ecp). all lpc devices supporting ecp must meet t he requirements contained in this section or the port will not be supported by microsoft. for a description of the ec p protocol, please refer to the ieee 1284 extended capabilities port protocol and isa interface standard , rev. 1.14, july 14, 1993. this document is available from microsoft. description the port is software and hardware compatible with ex isting parallel ports so t hat it may be used as a standard lpt port if ecp is not require d. the port is designed to be si mple and requires a small number of gates to implement. it does not do any "protocol" nego tiation, rather it pr ovides an automatic high burst-bandwidth channel that supports dma for ec p in both the forward and reverse directions. small fifos are employed in both forward and reverse directions to smooth data flow and improve the maximum bandwidth requirement. the size of the fifo is 16 bytes deep. the port supports an automatic handshake for the standard parallel port to im prove compatibility m ode transfer speed. the port also supports run length encoded (rle) dec ompression (required) in hardware. compression is accomplished by counting identical bytes and transmitting an rle byte that indicates how many times the next byte is to be repeated. decomp ression simply intercepts the rle byte and repeats the following byte the specified number of times. hardware support for compression is optional.
99 table 37 - ecp pin descriptions name type description nstrobe o during write operations nstrobe regi sters data or address into the slave on the asserting edge (handshakes with busy). pdata 7:0 i/o contains addr ess or data or rle data. nack i indicates valid data driven by t he peripheral when asserted. this signal handshakes with nautofd in reverse. periphack (busy) i this signal deasserts to indi cate that the peripheral can accept data. this signal handshakes with nstrobe in the forward direction. in the reverse direction this signal indicates whet her the data lines contain ecp command information or data. the peripheral uses this signal to flow control in the forward direction. it is an "interlo cked" handshake with nstrobe. periphack also provides command information in the reverse direction. perror (nackreverse) i used to acknowledge a change in the direction the transfer (asserted = forward). the peripheral drives this signal low to acknowledge nreverserequest. it is an "interlocked" handshake with nreverserequest. the host relies upon nackreverse to determine when it is permitted to drive the data bus. select i indicates printer on line. nautofd (hostack) o requests a byte of data from t he peripheral when asserted, handshaking with nack in the reverse direction. in the forward direction this signal indicates whether the data lines cont ain ecp address or data. the host drives this signal to flow control in t he reverse direction. it is an "interlocked" handshake with nack. hostack also pr ovides command information in the forward phase. nfault (nperiphrequest) i generates an error interrupt when asserted. this signal provides a mechanism for peer-to-peer communication. this signal is valid only in the forward direction. during ecp mode the peripheral is permitted (but not required) to drive this pin low to re quest a reverse transfer. the request is merely a "hint" to the host; the host has ultimate control over the transfer direction. this signal would be typica lly used to generate an interrupt to the host cpu. ninit o sets the transfer direction (assert ed = reverse, deasserted = forward). this pin is driven low to place the chan nel in the reverse direction. the peripheral is only allowed to drive t he bi-directional data bus while in ecp mode and hostack is low and nselectin is high. nselectin o always deasserted in ecp mode. register definitions the register definitions ar e based on the standard ibm addresses for lp t. all of the standard printer ports are supported. the additional register s attach to an upper bit decode of the standard lpt port definition to avoid conflict with standard isa devices . the port is equivalent to a generic parallel port interface and may be operated in that mode. the port regi sters vary depending on the mode fi eld in the ecr. the table below lists these dependencies. operation of the devices in modes other t hat those specif ied is undefined.
100 table 38 - ecp register definitions name address (note 1) ecp modes function data +000h r/w 000-001 data register ecpafifo +000h r/w 011 ecp fifo (address) dsr +001h r/w all status register dcr +002h r/w all control register cfifo +400h r/w 010 parallel port data fifo ecpdfifo +400h r/w 011 ecp fifo (data) tfifo +400h r/w 110 test fifo cnfga +400h r 111 configuration register a cnfgb +401h r/w 111 configuration register b ecr +402h r/w all extended control register note 1: these addresses are added to the parallel port base address as selected by configuration register or jumpers. note 2: all addresses are qualified with aen. refer to the aen pin definition. table 39 - mode descriptions mode description* 000 spp mode 001 ps/2 parallel port mode 010 parallel port data fifo mode 011 ecp parallel port mode 100 epp mode (if this option is enabled in the configurat ion registers) 101 reserved 110 test mode 111 configuration mode *refer to ecr register description data and ecpafifo port address offset = 00h modes 000 and 001 (data port) the data port is located at an offset of '00h' fr om the base address. the dat a register is cleared at initialization by reset. during a write operation, the data register latches the contents of the data bus. the contents of this regi ster are buffered (non inverting) and out put onto the pd0 - pd7 ports. during a read operation, pd0 - pd7 ports are read and output to the host cpu. mode 011 (ecp fifo - address/rle) a data byte written to this address is placed in the fifo and tagged as an ecp address/rle. the hardware at the ecp port transmits th is byte to the peripheral automatica lly. the operation of this register is ony defined for the forward direction (direction is 0). refer to the ecp parallel port forward timing diagram, located in the timing diagr ams section of this data sheet .
101 device status register (dsr) address offset = 01h the status port is located at an offset of '01h' from the base addr ess. bits 0 - 2 are not implemented as register bits, during a read of the prin ter status register these bits are a low level. the bits of the status port are defined as follows: bit 3 nfault the level on the nfault input is read by the cpu as bit 3 of the device status register. bit 4 select the level on the select input is read by the cpu as bit 4 of the device status register. bit 5 perror the level on the perror input is read by the cpu as bit 5 of the device status r egister. printer status register. bit 6 nack the level on the nack input is read by the cpu as bit 6 of the device status register. bit 7 nbusy the complement of the level on the busy input is read by the cpu as bit 7 of the device status register. device control register (dcr) address offset = 02h the control register is located at an offset of '02h' from the base address. the control register is initialized to zero by the reset input, bits 0 to 5 only being affected; bits 6 and 7 are hard wired low. bit 0 strobe - strobe this bit is inverted and output onto the nstrobe output. bit 1 autofd - autofeed this bit is inverted and output ont o the nautofd output. a logic 1 c auses the printer to generate a line feed after each line is printed. a logic 0 means no autofeed. bit 2 ninit - ninitiate output this bit is output onto the ni nit output without inversion. bit 3 selectin this bit is inverted and output onto t he nslctin output. a logic 1 on this bit selects the printer; a logic 0 means the printer is not selected. bit 4 ackinten - interrupt request enable the interrupt request enable bit when set to a high level may be used to enable interrupt requests from the parallel port to the cpu due to a low to high trans ition on the nack input. refer to the description of the interrupt under oper ation, interrupts. bit 5 direction if mode=000 or mode=010, this bit has no effect and the di rection is always out regardless of the state of this bit. in all other modes, direction is valid and a logic 0 means that the pr inter port is in output mode (write); a logic 1 means that the pr inter port is in input mode (read).
102 bits 6 and 7 during a read are a low le vel, and cannot be written. cfifo (parallel port data fifo) address offset = 400h mode = 010 bytes written or dmaed from the system to this fifo are transmitted by a hardware handshake to the peripheral using the standard parallel port protocol. transfers to the fifo are byte aligned. this mode is only defined for the forward direction. ecpdfifo (ecp data fifo) address offset = 400h mode = 011 bytes written or dmaed from the system to this fif o, when the direction bit is 0, are transmitted by a hardware handshake to the peripheral us ing the ecp parallel port protocol. transfers to the fifo are byte aligned. data bytes from the peripheral are read under autom atic hardware handshake from ecp into this fifo when the direction bit is 1. reads or dmas from t he fifo will return bytes of ecp data to the system. tfifo (test fifo mode) address offset = 400h mode = 110 data bytes may be read, written or dma ed to or from the system to this fi fo in any direction. data in the tfifo will not be transmitted to the to the paralle l port lines using a hardw are protocol handshake. however, data in the tfifo may be displayed on the parallel port data lines. the tfifo will not stall when overwri tten or underrun. if an attempt is m ade to write data to a full tfifo, the new data is not accepted into the tfifo. if an attemp t is made to read data from an empty tfifo, the last data byte is re-read again. the full and empty bits must always keep tra ck of the correct fifo state. the tfifo will transfer data at the maximum isa rate so that software may generate performance metrics. the fifo size and interrupt threshold can be determi ned by writing bytes to the fifo and checking the full and serviceintr bits. the writeintrthreshold can be determi ned by starting with a full tfifo, setting the direction bit to 0 and emptying it a byte at a time until se rviceintr is set. this may generate a spurious interrupt, but will indicate that the threshold has been reached. the readintrthreshold can be determined by setting the di rection bit to 1 and filling the empty tfifo a byte at a time until serviceintr is set. this may generate a spurious interrupt, but will indicate that the threshold has been reached. data bytes are always read from the head of tfifo re gardless of the value of the direction bit. for example if 44h, 33h, 22h is written to the fif o, then reading the tfifo will return 44h, 33h, 22h in the same order as was written.
103 cnfga (configuration register a) address offset = 400h mode = 111 this register is a read only register. when read, 10h is returned. this i ndicates to the system that this is an 8-bit implementation. (pword = 1 byte) cnfgb (configuration register b) address offset = 401h mode = 111 bit 7 compress this bit is read only. during a read it is a low leve l. this means that this chip does not support hardware rle compression. it does support hardware de-compression! bit 6 intrvalue returns the value of the interrupt to determine possible conflicts. bits [5:3] parallel po rt irq (read-only) refer to table 40b. bits [2:0] parallel port dma (read-only) refer to table 40c. ecr (extended control register) address offset = 402h mode = all this register controls the ex tended ecp parallel port functions. bits 7,6,5 these bits are read/writ e and select the mode. bit 4 nerrintren read/write (valid only in ecp mode) 1: disables the interr upt generated on the asserting edge of nfault. 0: enables an interrupt pulse on the high to low edge of nfault. note that an in terrupt will be generated if nfault is asserted (interrupting) and this bit is wri tten from a 1 to a 0. this prevents interrupts from being lost in the time between the read of the ecr and the wr ite of the ecr. bit 3 dmaen read/write 1: enables dma (dma starts when serviceintr is 0). 0: disables dma unconditionally. bit 2 serviceintr read/write 1: disables dma and all of the service interrupts. 0: enables one of the following 3 ca ses of interrupts. once one of t he 3 service interrupts has occurred serviceintr bit shall be set to a 1 by hardware. it mu st be reset to 0 to re-enabl e the interrupts. writing this bit to a 1 will not cause an interrupt. case dmaen=1:
104 during dma (this bit is set to a 1 when terminal count is reached). case dmaen=0 direction=0: this bit shall be set to 1 whenever there are wr iteintrthreshold or more bytes free in the fifo. case dmaen=0 direction=1: this bit shall be set to 1 whenever there are readint rthreshold or more valid bytes to be read from the fifo. bit 1 full read only 1: the fifo cannot accept another byte or the fifo is completely full. 0: the fifo has at least 1 free byte. bit 0 empty read only 1: the fifo is completely empty. 0: the fifo contains at least 1 byte of data.
105 table 40a - extended control register r/w mode 000: standard parallel port mode . in this mode t he fifo is reset and common collector drivers are used on the control lines (n strobe, nautofd, ninit and nselec tin). setting the direction bit will not tri-state the outpu t drivers in this mode. 001: ps/2 parallel port mode. same as above except that direction may be used to tri-state the data lines and reading the data register return s the value on the data lines and not the value in the data register. all driver s have active pull-ups (push-pull). 010: parallel port fifo mode. this is the same as 000 except that bytes are written or dmaed to the fifo. fifo data is automatically transmi tted using the standard parallel port protocol. note that this mode is only useful when direct ion is 0. all drivers have active pull-ups (push-pull). 011: ecp parallel port mode. in the forward direction (direction is 0) bytes placed into the ecpdfifo and bytes written to the ecpafifo are placed in a single fifo and transmitted automatically to the peripheral using ecp protocol. in the revers e direction (direction is 1) bytes are moved from the ecp parallel port and packed into byte s in the ecpdfifo. all drivers have active pull-ups (push-pull). 100: selects epp mode: in this mode, epp is sele cted if the epp supported option is selected in configuration register cr04 (bits[ 1,0] and bit[6]). all drivers have active pull-ups (push-pull). 101: reserved 110: test mode. in this mode the fifo ma y be written and read, but the data will not be transmitted on the parallel port. all dr ivers have active pull-ups (push-pull). 111: configuration mode. in this mode the confga, confgb regi sters are accessible at 0x400 and 0x401. all drivers have active pull-ups (push-pull). table 40b table 40c irq selected cnfgb bits [5:3] dma selected cnfgb bits [2:0] 15 110 3 011 14 101 2 010 11 100 1 001 10 011 all others 000 9 010 7 001 5 111 all others 000 operation mode switching/software control software will execute p1284 negotiation and all operati on prior to a data transf er phase under programmed i/o control (mode 000 or 001). hardware provides an automatic control line handshake, moving data between the fifo and the ecp port only in the data transfer phase (modes 011 or 010). setting the mode to 011 or 010 will cause the hardware to in itiate data transfer. if the port is in mode 000 or 001 it may switch to any other mode. if the port is not in mode 000 or 001 it can only be switched into mode 000 or 001. the direction can only be changed in mode 001.
106 ecp operation prior to ecp operation the host must negotiate on the parallel port to dete rmine if the peripheral supports the ecp protocol. this is a somewhat complex negot iation carried out under program control in mode 000. after negotiation, it is necessary to initialize so me of the port bits. the following are required: set direction = 0, enabling the drivers. set strobe = 0, causing the nstrobe sig nal to default to the deasserted state. set autofd = 0, causing the nautofd sign al to default to the deasserted state. set mode = 011 (ecp mode) ecp address/rle bytes or data bytes may be sent autom atically by writing the ecpafifo or ecpdfifo respectively. note that all fifo data transfers are byte wide and by te aligned. address/rle transfers are byte-wide and only allowed in the forward direction. the host may switch directions by first switching to mode = 001, negotiating for the forward or reverse channel, setting direction to 1 or 0, then setting m ode = 011. when direction is 1 the hardware shall handshake for each ecp read data byte and attempt to f ill the fifo. bytes may then be read from the ecpdfifo as long as it is not empty. ecp transfers may also be accomplished (albeit slowly) by handshaking individual bytes under program control in mode = 001, or 000. termination from ecp mode termination from ecp mode is similar to the terminat ion from nibble/byte modes. the host is permitted to terminate from ecp mode only in sp ecific well-defined states. the te rmination can only be executed while the bus is in the forward direction. to terminate while the channel is in the reverse direction, it must first be transitioned into the forward direction. command/data ecp mode supports two advanced features to improv e the effectiveness of the protocol for some applications. the features are impl emented by allowing the transfer of normal 8 bit data or 8 bit commands. when in the forward direction, normal data is trans ferred when hostack is high and an 8 bit command is transferred when hostack is low. the most significant bit of the command indicates whet her it is a run-length count (for compression) or a channel address. when in the reverse direction, normal data is transfe rred when periphack is high and an 8 bit command is transferred when periphack is low. the most signific ant bit of the command is always zero. reverse channel addresses are seldom used and may not be supported in hardware.
107 table 41 - forward channel commands (hostack low) reverse channel commands (peripack low) d7 d[6:0] 0 run-length count (0-127) (mode 0011 0x00 only) 1 channel address (0-127) data compression the ecp port supports run length encoded (rle) decompression in hardware and can transfer compressed data to a peripheral. run length encoded (r le) compression in hardware is not supported. to transfer compressed data in ecp mode, the compre ssion count is written to the ecpafifo and the data byte is written to the ecpdfifo. compression is accomplished by counting identical byte s and transmitting an rle byte that indicates how many times the next byte is to be repeated. deco mpression simply intercepts the rle byte and repeats the following byte the specified number of times. when a run-length count is received from a peripheral, the subsequent data byte is replic ated the specified number of times. a r un-length count of ze ro specifies that only one byte of data is represented by the next data byte, whereas a run- length count of 127 indicates that the next byte should be expanded to 128 bytes. to prev ent data expansion, however , run-length counts of zero should be avoided. pin definition the drivers for nstrobe, nautofd, ninit and nselectin are open-collector in mode 000 and are push-pull in all other modes. lpc connections the interface can never stall causing the host to hang. the width of data transfers is strictly controlled on an i/o address basis per this specificat ion. all fifo-dma transfers are byte wide, byte aligned and end on a byte boundary. (the pword value can be obtained by r eading configuration regist er a, cnfga, described in the next section). single byte wide transfers are always possible with standard or ps/2 mode using program control of the control signals. interrupts the interrupts are enabled by serv iceintr in the ecr register. serviceintr = 1 disables the dma and all of the service interrupts. serviceintr = 0 enables the sele cted interrupt condition. if the in terrupting condition is valid, then the interrupt is generated immediately when this bit is changed from a 1 to a 0. this can occur during programmed i/o if the number of bytes removed or added from/to the fifo does not cross the threshold. an interrupt is generated when: 1. for dma transfers: when serviceintr is 0, dm aen is 1 and the dma tc cycle is received. 2. for programmed i/o: a. when serviceintr is 0, dmae n is 0, direction is 0 and there ar e writeintrthreshold or more free bytes in the fifo. also, an interrupt is genera ted when serviceintr is cleared to 0 whenever there are writeintrthreshold or more free bytes in the fifo.
108 b. when serviceintr is 0, dmaen is 0, direction is 1 and there are re adintrthreshold or more bytes in the fifo. also, an interrupt is generated when serviceintr is cleared to 0 whenever there are readintrthreshold or more bytes in the fifo. 3. when nerrintren is 0 and nfault tran sitions from high to low or when nerrintren is set from 1 to 0 and nfault is asserted. 4. when ackinten is 1 and the nack signal transitions from a low to a high. fifo operation the fifo threshold is set in the chip configuration regi sters. all data transfers to or from the parallel port can proceed in dma or programmed i/o (non-dma) mode as indicated by t he selected mode. the fifo is used by selecting the parallel port fifo mode or ecp parallel po rt mode. (fifo test mode will be addressed separately.) after a reset, the fifo is disabled. each data byte is transferred by a programmed i/o cycle or dma cycle depending on the selection of dma or programmed i/o mode. the following paragraphs detail the operat ion of the fifo flow control. in these descriptions, ranges from 1 to 16. the parameter fifothr, which the user programs, is one less and ranges from 0 to 15. a low threshold value (i.e. 2) results in longer periods of time between service r equests, but requires faster servicing of the request for both r ead and write cases. the host must be very responsive to the service request. this is the desired case for use with a "fast" system. a high value of threshold (i.e. 12) is used with a "sluggish" system by affording a long latenc y period after a service request, but results in more frequent service requests. dma transfers dma transfers are always to or from the ecpdfifo , tfifo or cfifo. dma utilizes the standard pc dma services. to use the dma transfers, the host first se ts up the direction and stat e as in the programmed i/o case. then it programs the dma cont roller in the host with the desired count and memory address. lastly it sets dmaen to 1 and serviceintr to 0. the ecp r equests dma transfers from the host by encoding the nldrq pin. the dma will empty or fill the fifo using the appropriate direction and mode. when the terminal count in the dma controller is reached, an in terrupt is generated and se rviceintr is asserted, disabling dma. in order to prevent possible blocki ng of refresh requests a dma cycle shall not be requested for more than 32 dma cycles in a row. the fifo is enabled directly by the host initiating a dma cycle for the requested channel, and addresses need not be valid. an interrupt is generated when a tc cycle is received. (note: the only way to proper ly terminate dma transfers is with a tc cycle.) dma may be disabled in the middle of a transfer by first disabling the host dma controller. then setting serviceintr to 1, followed by setting dmaen to 0, and waiting for the fifo to become empty or full. restarting the dma is accomplished by enabling dma in the host, setting dmaen to 1, followed by setting serviceintr to 0. dma mode - transfers from the fifo to the host (note: in the reverse mode, the peripheral may not continue to fill the fi fo if it runs out of data to transfer, even if the chip continues to reques t more data from the peripheral.) the ecp requests a dma cycle whenever there is data in the fifo. the dma controller responds to the request by reading data from the fifo. the ecp st op requesting dma cycles when the fifo becomes empty or when a tc cycle is received, indicating that no more data is required. if the ecp stops requesting dma cycles due to the fifo going empty, then a dm a cycle is requested again as soon as there is one byte in the fifo. if the ecp stops requesting dm a cycles due to the tc cycle, then a dma cycle is requested again when there is one byte in the fifo, and serviceintr has been re-enabled.
109 programmed i/o mode or non-dma mode the ecp or parallel port fifos may also be operated using interrupt driven programmed i/o. software can determine the writeintrthres hold, readintrthreshold, and fifo depth by accessing the fifo in test mode. programmed i/o transfers are to the ecpdfifo at 400h and ecpafifo at 000h or from the ecpdfifo located at 400h, or to/from the tfifo at 400h. to use the programmed i/o tran sfers, the host first sets up the direction and state, sets dmae n to 0 and serviceintr to 0. the ecp requests programmed i/o transfers from the hos t by activating the interrupt. the programmed i/o will empty or fill the fifo using the appropriate direction and mode. note: a threshold of 16 is equiva lent to a threshold of 15. these two cases are treated the same. programmed i/o - transfers from the fifo to the host in the reverse direction an interrupt occurs when serv iceintr is 0 and readintrthr eshold bytes are available in the fifo. if at this time the fifo is full it can be emptied completely in a single burst, otherwise readintrthreshold bytes may be read from the fifo in a single burst. readintrthreshold =(16-) data bytes in fifo an interrupt is generated when serviceint r is 0 and the number of bytes in t he fifo is greater than or equal to (16-). (if the threshol d = 12, then the interrupt is set wh enever there are 4-16 bytes in the fifo). the host must respond to the request by readi ng data from the fifo. this process is repeated until the last byte is transferred out of the fifo. if at th is time the fifo is full, it can be completely emptied in a single burst, otherwise a minimum of (16-) bytes may be read from the fifo in a single burst. programmed i/o - transfers from the host to the fifo in the forward direction an interrupt occurs when serv iceintr is 0 and there are wr iteintrthreshold or more bytes free in the fifo. at this time if the fifo is empty it can be filled with a single burst before the empty bit needs to be re-read. otherwise it may be filled with writeintrthreshold bytes. writeintrthreshold = (16-) free bytes in fifo an interrupt is generated when servicei ntr is 0 and the number of bytes in the fifo is less than or equal to . (if the threshold = 12, then the interrupt is set whenever there are 12 or less bytes of data in the fifo.) the host must respond to the request by writi ng data to the fifo. if at this time the fifo is empty, it can be completely filled in a single burst, otherwise a minimum of (16-) bytes may be written to the fifo in a single burst. this process is re peated until the last byte is transferred into the fifo. parallel port floppy disk controller the floppy disk control signals are available optiona lly on the parallel port pins. when this mode is selected, the parallel port is not available. there are two modes of operation, ppfd1 and ppfd2. these modes can be selected in the parallel and seri al extended setup register (cr04). ppfd1 has only drive 1 on the parallel port pins; ppfd2 has drive 0 and 1 on the parallel port pins. see the configuration section for description of the register. the fdc_pp pin can be used to switch the parallel port pins between the fdc and the parallel port functions. see the following sub-section. the following parallel port pins are read as follo ws by a read of the parallel port register: 1. data register (read) = la st data register (write)
110 2. control register read as "cable not connected" strobe, au tofd and slc = 0 and ninit =1 3. status register reads: nbusy = 0, pe = 0, slct = 0, nack = 1, nerr = 1 the following fdc pins are all in the high impedence state when the ppfdc is ac tually selected by the drive select register: 1. nwdata, densel, nhdsel, nwgate, ndir , nstep, nds1, nds0, nmtr0, nmtr1. 2. if ppfdx is selected, then the parallel port can not be used as a par allel port until "normal" mode is selected. the fdc signals are muxed onto the paralle l port pins as shown in table 43. for acpi compliance the fdd pins that are multiplexed onto the parallel port function independently of the state of the parallel po rt controller. for exam ple, if the fdc is enabled onto the parallel port the multiplexed fdd interface functions normally regardle ss of the parallel port po wer control, cr01.2. table 42 illustrates this functionality. table 42 - modified parallel port fdd control parallel port power parallel port fdc control parallel port fdc state parallel port state cr01.2 cr04.3 cr04.2 1 0 0 off on 0 0 0 off off x 1 x on off x 1 (note 1 ) note 1 : the parallel port control register reads as ?cable not connected? when the parallel port fdc is enabled; i.e., strobe = autofd = slc = 0 and ninit = 1.
111 table 43 ? fdc parallel port pins connecto r pin # chip pin # spp mode pin direction fdc mode pin direction 1 83 nstrobe i/o (nds0) i/(o) note1 2 68 pd0 i/o nindex i 3 69 pd1 i/o ntrk0 i 4 70 pd2 i/o nwp i 5 71 pd3 i/o nrdata i 6 72 pd4 i/o ndskchg i 7 73 pd5 i/o - - 8 74 pd6 i/o (nmtr0) i/(o) note1 9 75 pd7 i/o - - 10 80 nack i nds1 o 11 79 busy i nmtr1 o 12 78 pe i nwdata o 13 77 slct i nwgate o 14 82 nalf i/o drvden0 o 15 81 nerror i nhdsel o 16 66 ninit i/o ndir o 17 67 nslctin i/o nstep o note 1: these pins are outputs in mode ppfd2, inputs in mode ppfd1. fdc on parallel port pin the ?floppy on the parallel port? pi n function, fdc_pp, is muxed ont o gp23. this pin function can be used to switch the parallel port pins between t he fdc and the parallel port. the fdc_pp pin can generate a pme and an smi by enabling gp23 in the appropriate pme and smi enable registers (bit 5 of pme_en2 and bit 4 of smi_en2 ? see the runtim e registers section). this pin generates an smi and pme on both a low-to-high and a high-to-low edge. the pin function for gp23 and the polar ity of gp23 is selected through gp io polarity register 2. when the fdc_pp function is selected, the pin must also be selected as an input via bit 3 of the gpio direction register 2. if the floppy_pp bits, cr21 bits[1:0] = 01 or 10, and the fdc_pp function is selected on gp23, then the default functionality (non-in verted polarity) for this pin is as fo llows: when the pin is low, the parallel port pins are used for a floppy disk controller; when t he pin is high, the parallel port pins are used for a parallel port. the polarity bit cont rols the state of the pin. if the floppy_pp bits, cr21 bits[1:0]=00 then the pin is not used to switch the parallel port pins between the fdc and the parallel port, even if the fdc_pp function is selected on gp23. see the configuration section for register description. note: when the floppy is selected on the parallel port, the parallel port irq, smi and the parallel port drq will not come out of the part.
112 power management power management capabilities are provided for the follo wing logical devices: floppy disk, uart 1, uart 2 and the parallel port. for each logical device, tw o types of power management are provided: direct powerdown and auto powerdown. fdc power management direct power management is controlled by bit[3] in cr 00. refer to the configuration section for more information. auto power management is enabled by bit[7] in cr07. w hen set, this bit allows fdc to enter powerdown when all of the following conditions have been met: 1. the motor enable pins of register 3f2h are inactive (zero). 2. the part must be idle; msr=80h and int = 0 (i nt may be high even if msr = 80h due to polling interrupts). 3. the head unload timer must have expired. 4. the auto powerdown timer (10msec) must have timed out. an internal timer is initiated as soon as the auto powerdown command is enabl ed. the part is then powered down when all the conditions are met. disabling the auto powerdown mode cancels the timer and holds the fdc block out of auto powerdown. dsr from powerdown if dsr powerdown is used when the part is in auto pow erdown, the dsr powerdown will override the auto powerdown. however, when the part is awakened from dsr powerdown, the auto powerdown will once again become effective. wake up from auto powerdown if the part enters the powerdown st ate through the auto powerdown m ode, then the part can be awakened by reset or by appropriate access to certain registers. if a hardware or software reset is used then the pa rt will go through the normal reset sequence. if the access is through the selected regi sters, then the fdc resumes oper ation as though it was never in powerdown. besides activating the np ci_reset pin or one of the software reset bits in the dor or dsr, the following register accesses will wake up the part: 1. enabling any one of the motor enable bits in the dor register (reading t he dor does not awaken the part). 2. a read from the msr register. 3. a read or write to the data register. once awake, the fdc will reinitiate the auto powerdown timer for 10 ms. the part will powerdown again when all the powerdown conditions are satisfied. register behavior table 44 illustrates the at and ps/2 (including model 30) configuration registers available and the type of access permitted. in order to ma intain software transparency, access to all the registers must be
113 maintained. as table 44 shows, two sets of regi sters are distinguished bas ed on whether their access results in the part remaining in powerdown state or exiting it. access to all other registers is possible without aw akening the part. these registers can be accessed during powerdown without changing the st atus of the part. a read from t hese registers will reflect the true status as shown in the register descr iption in the fdc description. a writ e to the part will result in the part retaining the data and subsequently reflecting it when the part awakens. accessing the part during powerdown may cause an increase in the power consum ption by the part. the part will revert back to its low power mode when the access has been completed. pin behavior the lpc47n227 is specifically designed for systems in which power conservation is a primary concern. this makes the behavior of the pins during powerdown very important. the pins of the lpc47n227 can be divided into two major categories: system interface and floppy disk drive interface. the floppy disk driv e pins are disabled so that no pow er will be drawn through the part as a result of any voltage applied to the pin within the part' s power supply range. most of the system interface pins are left active to monitor system accesses that may wake up the part. table 44 - pc/at and ps/2 available registers available registers base + address pc-at ps/2 (model 30) access permitted access to these registers does not wake up the part 00h ---- sra r 01h ---- srb r 02h dor (1) dor (1) r/w 03h --- --- --- 04h dsr (1) dsr (1) w 06h --- --- --- 07h dir dir r 07h ccr ccr w access to these registers wakes up the part 04h msr msr r 05h data data r/w note 1: writing to the dor or dsr does not wake up the part, however, writing any of the motor enable bits or doing a software reset (via dor or dsr reset bits) will wake up the part. system interface pins table 45 gives the state of the inte rface pins in the power down state. pins unaffe cted by the powerdown are labeled "unchanged". table 45 ? state of system pins in auto powerdown system pins state in auto powerdown lad[3:0] unchanged nldrq unchanged nlpcpd unchanged nlframe unchanged
114 npci_reset unchanged pci_clk unchanged ser_irq unchanged fdd interface pins all pins in the fdd interface whic h can be connected directly to the fl oppy disk drive itself are either disabled or tristated. pins used for local logic control or part programming are unaffected. table 46 depicts the state of the floppy disk drive interface pins in the powerdown state. table 46 - state of floppy disk drive interface pins in powerdown fdd pins state in auto powerdown input pins nrdata input nwrtprt input ntrk0 input nindex input ndskchg input output pins nmtr0 tristated nds0 tristated ndir active nstep active nwdata tristated nwgate tristated nhdsel active drvden[0:1] active uart power management direct power management is controlled by cr02. refer to the configuration section for more information. auto power management is enabled by the uart1 and uart 2 enable bits in cr07. when set, these bits allow the following auto pow er management operations: 1. the transmitter enters auto pow erdown when the transmit buffer and shift register are empty. 2. the receiver enters powerdown w hen the following conditions are all met: a. receive fifo is empty b. the receiver is waiting for a start bit. note: while in powerdown the ring indicator interrupt is still valid and transit ions when the ri input changes. exit auto powerdown the transmitter exits powerdown on a write to the xmit buffer. the receiver exits auto powerdown when rxdx changes state. parallel port
115 direct power management is controlled by bit[2] in cr 01. refer to the configuration section for more information. auto power management is enabled by bit[4] in cr07 . when set, this bit allows the ecp or epp logical parallel port blocks to be placed into powerdown when not being used. the epp logic is in powerdown under any of the following conditions: 1. epp is not enabled in the configuration registers. 2. epp is not selected through ecr while in ecp mode. the ecp logic is in powerdown under any of the following conditions: 1. ecp is not enabled in the configuration registers. 2 spp, ps/2 parallel port or epp mode is se lected through ecr while in ecp mode. exit auto powerdown the parallel port logic can change powerdown modes when the ecp mode is changed through the ecr register or when the parallel port mode is changed through the config uration registers.
116 serial irq the lpc47n227 supports the serial interrupt to trans mit interrupt information to the host system. the serial interrupt scheme adheres to the serial irq s pecification for pci system s, version 6.0. the pci_clk, ser_irq and nclkrun pins are used for th is interface. the serial irq/clkrun enable bit d7 in cr29 activates the serial interrupt interface. timing diagrams for ser_irq cycle a) start frame timing with source sampled a low pulse on irq1 rt s rt s ser_irq pci_clk host controller irq irq1 drive source rt none irq0 frame irq1 frame s rt irq2 frame none start start frame h sl or h 1 note: h=host control; r=recovery; t=tu rn-around; sl=slave control; s=sample note 1: start frame pulse can be 4-8 clocks wi de depending on the location of the device in the pci bridge hierarchy in a synchronous bridge design. b) stop frame timing with host using 17 ser_irq sampling period s rt s ser_irq pci_clk host controller irq15 driver rt none irq14 irq15 s rt iochck# none stop rt stop frame h i start next cycle 1 2 3 frame frame frame note: h=host control; r=recovery ; t=turn-around; s=sample; i=idle note 1: stop pulse is 2 clocks wide for qu iet mode, 3 clocks wide for continuous mode. note 2: there may be none, one or more idle states during the stop frame. note 3: the next ser_irq cycle?s start frame pulse may or may not start immediately after the turn- around clock of the stop frame.
117 ser_irq cycle control there are two modes of operation for the ser_irq start frame. 1) quiet (active) mode : any device may initiate a start fram e by driving the ser_irq low for one clock, while the ser_irq is idle. after driving lo w for one clock the ser_irq is immediately tri-stated without at any time driving high. a start frame may not be initiated while the ser_irq is active. the ser_irq is idle between stop and start frames. the ser_irq is active between start and stop frames. this mode of operation allo ws the ser_irq to be idle when there are no irq/data transitions which should be most of the time. once a start frame has been initiated the host controller will take over driving the ser_irq low in the next clock and will continue driving the ser_irq low for a programm able period of three to seven clocks. this makes a total low pulse width of four to eight clocks. finally, the host controller will drive the ser_irq back high for one clock, then tri-state. any ser_irq device (i.e., the lpc47n227) which det ects any transition on an irq/data line for which it is responsible must initiate a start frame in order to update the host controller unless the ser_irq is already in an ser_irq cycle and the irq/data tr ansition can be delivered in that ser_irq cycle. 2) continuous (idle) mode : only the host controller can initia te a start frame to update irq/data line information. all other ser_irq agents become passive and may not init iate a start frame. ser_irq will be driven low for four to eight clocks by host controller. this mode has two functions. it can be used to stop or idle the ser_irq or the host controller can operate ser_irq in a continuous mode by initiating a start frame at t he end of every stop frame. an ser_irq mode transition can only occur during the stop frame. upon reset, ser_irq bus is defaulted to continuous mode, therefore only the host controller can initiate the first start frame. slaves must continuously sample the stop frames pulse width to determine the next ser_irq cycle?s mode. ser_irq data frame once a start frame has been initia ted, the lpc47n227 will watch for the rising edge of the start pulse and start counting irq/data frames fr om there. each irq/data frame is three clocks: sample phase, recovery phase, and turn-around phase. during the sample phase the lpc47n227 drives the ser_irq low, if and only if, its last detected irq/data value was low. if its detected irq/data value is high, ser_irq is left tri-stated. during the recovery phase the lp c47n227 drives t he ser_irq high, if and only if, it had driven the ser _irq low during the previous sa mple phase. during the turn- around phase the lpc47n227 tri-st ates the ser_irq. the lpc47n 227 will drive the ser_irq line low at the appropriate sample point if its associated irq/data line is low, regardless of which device initiated the start frame. the sample phase for each irq/data follows the low to high transition of the start frame pulse by a number of clocks equal to the irq/data frame times thr ee, minus one. (e.g. the irq5 sample clock is the sixth irq/data frame, (6 x 3) - 1 = 17th clock after the rising edge of the start pulse).
118 ser_irq sampling periods ser_irq period signal sampled # of clocks past start 1 not used 2 2 irq1 5 3 nio_smi/irq2 8 4 irq3 11 5 irq4 14 6 irq5 17 7 irq6 20 8 irq7 23 9 irq8 26 10 irq9 29 11 irq10 32 12 irq11 35 13 irq12 38 14 irq13 41 15 irq14 44 16 irq15 47 the ser_irq data frame supports ir q2 from a logical device on peri od 3, which can be used for the system management interrupt (nsmi). when using pe riod 3 for irq2 the user should mask off the smi via the smi enable register. likewise, when using pe riod 3 for nsmi the user should not configure any logical devices as using irq2. ser_irq period 14 is used to transfer irq13. logical dev ices fdc, parallel port, serial port 1, serial port 2 have irq13 as a choice for their primary interrupt. the smi is enabled onto the smi frame of the serial irq via bit 6 of smi enable register 2 and onto the nio_smi pin via bit 7 of the smi enable register 2. stop cycle control once all irq/data frames have completed the host controller will terminate ser_irq activity by initiating a stop frame. only the ho st controller can initiate the stop frame. a stop frame is indicated when the ser_irq is low for two or three clocks. if the stop frame?s low time is two clocks then the next ser_irq cycle?s sampled mode is the quiet m ode; and any ser_irq device may initiate a start frame in the second clock or more after the risi ng edge of the stop frame?s pulse. if the stop frame?s low time is three clocks then the next ser_irq cy cle?s sampled mode is the continuos mode; and only the host controller may initiate a start frame in the second clock or more after the rising edge of the stop frame?s pulse. latency latency for irq/data updates over t he ser_irq bus in bridge-less sy stems with the minimum host supported irq/data frames of sevent een, will range up to 96 clocks (3.84 s with a 25mhz pci bus or 2.88us with a 33mhz pci bus). if one or more pci to pci bridge is added to a system, the latency for irq/data updates from the secondary or tertiary buses will be a few clocks longer for synchronous buses, and approximately double for asynchronous buses.
119 eoi/isr read latency any serialized irq scheme has a pot ential implementation issue relat ed to irq latency. irq latency could cause an eoi or isr read to precede an irq trans ition that it should hav e followed. this could cause a system fault. the host interrupt controller is responsible for ensuring t hat these latency issues are mitigated. the recommended solution is to delay e ois and isr reads to the interrupt controller by the same amount as the ser _irq cycle latency in order to ensur e that these event s do not occur out of order. ac/dc specification issue all ser_irq agents must drive / sa mple ser_irq synchronously relat ed to the rising edge of pci bus clock. the ser_irq pin uses the electrical specification of pci bus . electrical parameters will follow pci spec. section 4, sustained tri-state. reset and initialization the ser_irq bus uses npci_reset as its reset si gnal. the ser_irq pin is tri-stated by all agents while npci_reset is active. with reset, ser_irq sl aves are put into the (continuous) idle mode. the host controller is responsible for starting the initial ser_irq cycle to collect system?s irq/data default values. the system then follows with the continuous/quiet mode protocol (stop frame pulse width) for subsequent ser_irq cycles. it is host controller?s responsibility to provide the default values to 8259?s and other system logic before the first ser_irq cy cle is performed. for ser_irq system suspend, insertion, or removal application, the host c ontroller should be programmed into continuous (idle) mode first. this is to guarantee ser _irq bus is in idle state before the system configuration changes. routable irq inputs the routable irq input (irqinx) functions are on pins 51 (irqin1) and 52 (irqin2), muxed onto gp13 and gp14 respectively as inputs. the irqinx pin?s irq time slot in the serial irq stream is selected via a 4-bit control register for each irqin functi on (cr29 for irqin1, cr2a for irqin2). a value of 0000 disables the irq function. the part is able to generate a pme and an smi from bot h of the irq inputs through the gpio bits in the pme and smi status and enable regist ers. the edge is programmable through the polarity bit of the gpio control register. user note: in order to use an irq for one of the irqinx inputs that are mu xed on the gpio pins, the corresponding irq must not be used for any of the dev ices in the lpc47n227. otherwise contention may occur.
120 pci clkrun support overview the lpc47n227 supports the pci nclkrun signal. nclk run is used to indicate the pci clock status as well as to request that a stopped clock be st arted. the lpc47n227 nclkrun signal is on pin number 28. see figure 3 for an example of a typical system implementation using nclkrun. if the lpc47n227 sirq_clkrun_en signal is disabled, it will disable the nclkrun support related to nldrq in addition to disabling the ser_irq and the nclkrun associated with ser_irq. nclkrun is an open drain output and an input. refer to the pci mobile design guide rev 1.0 for a description of the nclkrun function. nclkrun for serial irq the lpc47n227 supports the pci nclkrun signal for the serial irqs. if an sio interrupt occurs while the pci clock is stopped, nclkrun is asserted before the serial interrupt signal is driven active. see ?using nclkrun? section below for more details. nclkrun for nldrq nclkrun support is also provided in the lpc47n227 for the nldrq signal. if a device requests dma service while the pci clock is stopped, nclkrun is asse rted to restart the pci clock. this is required to drive the nldrq signal active. see ?using nclkrun? section for more details. using nclkrun if nclkrun is sampled ?high?, the pci clock is st opped or stopping. if nclkrun is sampled ?low?, the pci clock is starting or started (running). if a device in the lpc47n227 asserts or de-asserts an interrupt or asserts a dma request, and nclkrun is sampled ?high?, the lpc47n227 requests the restoration of the clock by a sserting the nclkrun signal asynchronously (table 47). the lpc47n227 holds nclkrun low until it detects two rising edges of the clock. after the second clock edge, the lpc47n227 disables the open dr ain driver (figure 4). the lpc47n227 will not assert nclkrun under any condi tions if sirq_clkrun_en is inactive (?0?). the sirq_clkrun_en bit is d7 in cr29. the lpc47n227 will not assert nclkrun if it is already driven low by t he central resource; i.e., the pci clock generator in figure 3. the lpc47n 227 will not assert nclkrun unless the line has been deasserted for two successive clocks; i.e ., before the clock was stopped (figure 4).
121 table 47 ? lpc47n227 nclkrun function sirq_clkrun_en internal interrupts/ dma requests nclkrun action 0 x x none no change x none change/assertion 1 0 none 1 1 assert nclkrun 2 note 1 : ?change/assertion? means eithe r-edge change on any internal irqs routed to the sirq block or assertion of an internal dma request by a device in lpc47n227. the ?assertion? detection logic runs asynchronously to the pci clock and regardless of the serial irq mode; i.e., ?continuous? or ?quiet?. note 2 : the nclkrun signal is ?1? for at least two c onsecutive clocks before lpc47n227 asserts (?0?) it. figure 3 ? nclkrun system implementation example pci clock generator (central resource) master target kona nclkrun pci clk
122 figure 4 ? clock start illustration note 1: the signal ?any irq change/drq assert ion? is the same as ?change/assertion? in table 47. note 2: the lpc47n227 continually monitors the state of nclkrun to maintain the pci clock until an active ?any irq change/drq assertion? condi tion has been transferred to the host in a ser_irq/dma cycle. for example, if ?any irq change/drq assertion? is asserted before nclkrun is de-asserted ( not shown in figure 4), the lpc47n227 must assert nclkrun as needed until the ser_irq/d ma cycle has completed. pci_clk nclkrun sirq_clkrun_en any irq change/ drq assertion 1,2 nclkrun driven by lpc47n227 lpc47n227 stops driving nclkrun 2 clks min.
123 general purpose i/o the lpc47n227 provides a set of flexible input/output control functions to t he system designer through the 29 independently programmable g eneral purpose i/o pins (gpio). the gpio pins can perform basic i/o and many of them can be indivi dually enabled to generate an smi and a pme. gpio pins the following pins include gpio functiona lity as defined in the table below. table 48 ? gpio pin functionality pin name power well default on vtr por default on vcc por pme/smi function 6 gp24 vcc note 1 input programmable pme/smi 32 gp30 vcc note 1 input programmable pme 33 gp31 vcc note 1 input programmable pme 34 gp32 vcc note 1 input programmable pme 35 gp33 vcc note 1 input programmable pme 36 gp34 vcc note 1 input programmable pme 37 gp35 vcc note 1 input programmable pme 38 gp36 vcc note 1 input programmable pme 39 gp37 vcc note 1 input programmable pme 40 gp40 vcc input programmable - 41 gp41 vcc input programmable - 42 gp42 vcc input programmable - 43 gp43 vcc input programmable - 44 gp44 vcc input programmable - 45 gp45 vcc input programmable - 46 gp46 vcc input programmable - 47 gp47 vcc input programmable - 48 gp10 vcc note 1 input programmable pme/smi 49 gp11/sysopt vcc note 1 i nput programmable pme/smi 50 gp12/nio_smi vcc note 1 input programmable nio_smi/ pme/smi 51 gp13/irqin1 vcc note 1 input programmable pme/smi 52 gp14/irqin2 vcc note 1 input programmable pme/smi 54 gp15 vcc note 1 input programmable pme/smi 55 gp16 vcc note 1 input programmable pme/smi 56 gp17 vcc note 1 input programmable pme/smi 57 gp20 vcc note 1 input programmable pme 58 gp21 vcc note 1 input programmable pme 59 gp22 vcc note 1 input programmable pme 64 gp23/fdc_pp vcc note 1 input programmable pme/smi note 1: these pins have input buffers into the wakeup logic that are powered by vtr.
124 description each gpio port has a 1-bit data register. gpios are controlled by gpio control registers located in the configuration section. the data register for each gpio port is r epresented as a bit in one of the 8-bit gpio data registers, gp1 to gp4. the bits in these registers reflect t he value of the associated gpio pin as follows. pin is an input: the bit is the value of the gpio pin. pin is an output: the value written to the bit goes to the gpio pin. latched on read and write. the gpio dat a registers are located in the runtime register block; s ee the runtime registers section. the gpio ports with their alternate functions and configuration state register addresses are listed in table 49. table 49 ? general purpose i/o port assignments pin no. /qfp default function alternate function data register 1 data register bit no. register offset (hex) 48 gpio 0 49 gpio 1 50 gpio nio_smi 2 51 gpio irqin1 3 52 gpio irqin2 4 54 gpio 5 55 gpio 6 56 gpio gp1 7 0c 57 gpio 0 58 gpio 1 59 gpio 2 64 gpio fdc_pp 3 6 gpio 4 n/a reserved 5 n/a reserved 6 n/a reserved gp2 7 0d 32 gpio 0 33 gpio 1 34 gpio 2 35 gpio 3 36 gpio 4 37 gpio 5 38 gpio 6 39 gpio gp3 7 0e 40 gpio 0 41 gpio 1 42 gpio 2 43 gpio 3 44 gpio 4 45 gpio 5 46 gpio 6 47 gpio gp4 7 0f note 1: the gpio data registers are located at the offset shown from the runtime registers block address.
125 gpio control each gpio port has an 8-bit control register that cont rols the behavior of the pi n. these registers are defined in the configuration sect ion of this specification. each gpio port may be configured as either an input or an output. if the pin is configured as an output, it can be programmed as open-dr ain or push-pull. inputs and outputs can be configured as non- inverting or inverting. gpio direction registers det ermine the port direction, gpio polarity registers determine the signal polarity, and gpio output type register determines the output driver type select. the gpio output type register applies to ce rtain gpios (gp12-gp17 and gp20). the gpio direction, polarity and output type registers control the gpio pin w hen the pin is configured for the gpio function and when the pin is configured for the alternate function for all pins. the basic gpio configuration opti ons are summarized in table 50. table 50 - gpio configuration summary selected function direction bit polarity bit description b0 b1 gpio 0 0 pin is a non-inverted output. 0 1 pin is an inverted output. 1 0 pin is a non-inverted input. 1 1 pin is an inverted input. gpio operation the operation of the gpio ports is illustrated in figure 5.
126 gpio pin gpio data register bit-n sd-bit gpx read gpio configuration register bit-1 (polarity) gpio configuration register bit-0 (input/output) 1 0 d-type transparent gpx write dq qd figure 5 - gpio function illustration note: figure 5 is for illustration purposes only and in not intended to suggest specific implementation details. when a gpio port is programmed as an input, reading it through the gpio data regi ster latches either the inverted or non-inverted logic va lue present at the gpio pin. writing to a gpio port that is programmed as an input has no effect (table 51). when a gpio port is programmed as an output, the logi c value or the inverted logic value that has been written into the gpio data register is output to the gpio pin. reading from a gpio port that is programmed as an output returns the last val ue written to the data register (table 51). table 51 ? gpio read/write behavior host operation gpio input port gpio output port read latched value of gpio pin last write to gpio data register write no effect bit placed in gpio data register the lpc47n227 provides 21 gpios that can direct ly generate a pme. see the table in the next section. the gpio polarity registers in the conf iguration section select the edge on these gpio pins that will set the associated status bit in the pme_sts1 ? pme_sts3 registers. the default is the low- to-high edge. if the corresponding enable bit in t he pme_en1 ? pme_en3 registers and the pme_en bit in the pme_en register is set, a pme will be gener ated. these registers are located in the runtime registers block, which is locat ed at the address contained in the c onfiguration regist ers cr30. the
127 pme status bits for the gpios are cleared on a writ e of ?1?. in addition, the lpc47n227 provides 10 gpios that can directly generate an smi. see the table in the next section. gpio pme and smi functionality the following gpios are dedicated wakeup gpios with a status and enable bit in the pme status and enable registers: gp10-gp17 gp20-gp24 gp30-gp37 this following is the list of pme status and enable registers for their corresponding gpios: pme_sts1 and pme_en1 for gp10-gp17 pme_sts2 and pme_en2 for gp20-gp24 pme_sts3 and pme_en3 for gp30-gp37 the following gpios can directly generate an smi and have a status and enable bi t in the smi status and enable registers. gp10-gp17 gp23, gp24 the following smi status and enable registers for these gpios: smi_sts1 and smi_en1 for gp10-17 smi_sts2 and smi_en2 for gp23-gp24
128 the following table summarizes the pme and smi functionality for each gpio. gpio pme smi output buffer power notes gp10-gp11 yes yes vcc gp12 yes yes/nio_smi vcc 1 gp13-gp17 yes yes vcc gp20-gp22 yes no vcc gp23-gp24 yes yes vcc gp30-gp37 yes no vcc gp40-gp47 no no vcc 2 note 1: since gp12 can be used to generate an smi and as the nio_smi output, do not enable gp12 to generate an smi (by setting bit 2 of the smi e nable register 1) if the nio_smi function is selected on the gp12 pin. use gp12 to generat e an smi event only if the smi output is enabled on the serial irq stream. note 2: gp40-gp47 should not be connected to any vt r powered external circuitry. these pins are not used for wakeup.
129 system management interrupt (smi) the lpc47n227 implements a ?group? nio_smi output pin. the sy stem management interrupt is a non-maskable interrupt with the highest priority level used for os transparent power management. the nsmi group interrupt output consists of the enabled interrupts from super i/o device interrupts (parallel port, serial port 1 and 2 and fdc) and many of t he gpios pins. the gp12/nio_smi pin, when selected for the nio_smi function, can be programmed to be ac tive high or active low via bit 2 in the gpio polarity register 1 (cr32). the nio_smi pin functi on defaults to active low. the output buffer type of the pin can be programmed to be open-drain or pus h-pull via gpio output type register (cr39). the interrupts are enabled onto the group nsmi output via the smi e nable registers 1 and 2. the nsmi output is then enabled ont o the nio_smi output pin via bit[7] in the smi enable register 2. the smi output can also be enabled onto the serial irq stream (irq2) via bi t[6] in the smi enable register 2. smi registers the smi event bits for the gpios events are locat ed in the smi status and e nable registers 1 and 2. the polarity of the edge used to set the status bit and generate an smi is controlled by the gpio polarity registers located in the c onfiguration section. for non-invert ed polarity (default) the status bit is set on the low-to-high edge. status bits for the gpios are cleared on a write of ?1?. the smi logic for the gpio events is implemented such t hat the output of the status bit for each event is combined with the corresponding enable bit in order to generate an smi. the smi event bits for the super i/o devices are loca ted in the smi status and enable register 1 and 2. all of these status bits ar e cleared at the source; thes e status bits are not clear ed by a write of ?1?. the smi logic for these events is implemented such t hat each event is directly combined with the corresponding enable bit in order to generate an smi. see the ?runtime registers? sect ion for the definition of the smi status and enable registers.
130 pme support the lpc47n227 offers support for power management events (pmes), also referred to as system control interrupt (sci) events in an acpi system. a power managem ent event is indicated to the chipset via the assertion of the nio_pme signal. in the lpc47n227, the nio_pme is asserted by active transitions on the ring indicator inputs nri1 and nri2, and programmable edges on gpio pins. the nio_pme pin can be programmed to be active high or ac tive low via bit 5 in the gpio polarity register 2 (cr34). the nio_pme pin function defaults to ac tive low, open-drain output. the output buffer type of the pin can be programmed to be open-drain or push-pull via bit 7 in the gpio output type register (cr39). this pin is powered by vtr. see the conf iguration section for descr iption on these registers. pme functionality is controlled by the pme status and enable registers in the runt ime registers block, which is located at the address pr ogrammed in register 0x30 in the configuration section. the pme enable bit, pme_en, globally controls pme wake-up events. when pme_en is inactive, the nio_pme signal can not be asserted. when pme_en is assert ed, any wake source whose individual pme wake enable register bit is asserted can cause nio_pme to become asserted. the pme status register indicate s that an enabled wake source has o ccurred and if the pme_en bit is set, asserted the nio_pme signal. the pme status bit is asserted by active transitions of pme wake sources. pme_sts will become asserted independent of the state of the gl obal pme enable, pme_en. the following pertains to the pme status bits for each event: ? the output of the status bit fo r each event is combined with the corresponding enable bit to set the pme status bit. ? the status bit for any pending events must be clear ed in order to clear the pme_sts bit. status bits are cleared on a write of ?1?. for the gpio events, the polarit y of the edge used to set the st atus bit and generate a pme is controlled by the gpio polarity registers in the configuration section. for non-inverted polarity (default) the status bit is set on the low-to-high edge. status bits are cl eared on a write of ?1?. in the lpc47n227 the nio_pme pin can be programm ed to be an open drain, active low, driver. the lpc47n227 nio_pme pin is fully isolated from other external devices that might pull the nio_pme signal low; i.e., the nio_pme signal is capable of being driven high externally by another active device or pullup even when the lpc47n227 vcc is grounded, providing vtr power is active. pme registers the pme registers are run-time registers as follows. these registers are locat ed in system i/o space at an offset from runtime registers block, the address programmed at r egister 0x30 in t he configuration section. the following registers are for gpio pme events: ? pme wake status 1 (pme_sts1), pme wake enable 1 (pme_en1) ? pme wake status 2 (pme_sts2), pme wake enable 2 (pme_en2) ? pme wake status 3 (pme_sts3), pme wake enable 3 (pme_en3) see pme register description in the runtime registers section.
131 runtime registers runtime registers block summary the runtime registers are locat ed at the address programmed in t he runtime register block base address configuration register lo cated in cr30. the part performs 16-bit address qualification on the runtime register base address (bits[11:0] are decoded and bits[15:12] must be ze ro). the runtime register block may be located within the r ange 0x0100-0x0fff on 16-byte boundaries. decodes are disabled if the runtime r egister base address is located below 0x100. these registers are powered by vtr. table 52 - runtime register block summary register offset (hex) type hard reset vcc por vtr por register 00 r/w - - 0x00 pme_sts 01 r/w - - 0x00 pme_en 02 r/w - - 0x00 pme_sts1 03 r/w - - 0x00 pme_sts2 04 r/w - - 0x00 pme_sts3 05 r/w - - 0x00 pme_en1 06 r/w - - 0x00 pme_en2 07 r/w - - 0x00 pme_en3 08 r/w - - 0x00 smi_sts1 09 r/w note 1 note 1 0x01 note 1 smi_sts2 0a r/w - - 0x00 smi_en1 0b r/w - - 0x00 smi_en2 0c r/w - - 0x00 gp1 0d r/w - - 0x00 gp2 0e r/w - - 0x00 gp3 0f r/w - - 0x00 gp4 note: hard reset: npci_reset pin asserted. note: reserved bits return 0 on read. note 1: the parallel port interrupt defaults to 1 w hen the parallel port power bi t is cleared. when the parallel port is activated, pint follows the nack input.
132 runtime registers block description table 53 ? runtime registers block description name/default register offset description pme_sts default = 0x00 on vtr por 00 (r/w) bit[0] pme_status = 0 (default) = 1 set when lpc47n227 would normally assert the nio_pme signal, independent of the state of the pme_en bit. set when a bit in a pme wake status register and its associated enable bit set. bit[7:1] reserved pme_status is not affected by vcc por, soft reset or hard reset. writing a ?1? to pme_status will clear it and cause the lpc47n227 to stop asserti ng nio_pme, if enabled. writing a ?0? to pme_status has no effect. pme_en default = 0x00 on vtr por 01 (r/w) bit[0] pme_en = 0 nio_pme signal assertion is disabled (default) = 1 enables lpc47n227 to assert nio_pmesignal bit[7:1] reserved pme_en is not affected by vcc por, soft reset or hard reset pme_sts1 default = 0x00 on vtr por 02 (r/w) pme wake status register 1 this register indicates the state of the individual pme wake sources, independent of the individual source enables or the pme_en bit. if the wake source has asserted a wake event, the associated pme wake status bit will be a ?1?. bit[0] gp10 bit[1] gp11 bit[2] gp12 bit[3] gp13 bit[4] gp14 bit[5] gp15 bit[6] gp16 bit[7] gp17 the pme wake status register is not affected by vcc por, soft reset or hard reset. writing a ?1? to bit[7:0] will clear it. writing a ?0? to any bit in pme wake status register has no effect.
133 name/default register offset description pme_sts2 default = 0x00 on vtr por 03 (r/w) pme wake status register 2 this register indicates the state of the individual pme wake sources, independent of the individual source enables or the pme_en bit. if the wake source has asserted a wake event, the associated pme wake status bit will be a ?1?. bit[0] ri1 bit[1] ri2 bit[2] gp20 bit[3] gp21 bit[4] gp22 bit[5] gp23 bit[6] gp24 bit[7] reserved the pme wake status register is not affected by vcc por, soft reset or hard reset. writing a ?1? to bit[7:0] will clear it. writing a ?0? to any bit in pme wake status register has no effect. pme_sts3 default = 0x00 on vtr por 04 (r/w) pme wake status register 3 this register indicates the state of the individual pme wake sources, independent of the individual source enables or the pme_en bit. if the wake source has asserted a wake event, the associated pme wake status bit will be a ?1?. bit[0] gp30 bit[1] gp31 bit[2] gp32 bit[3] gp33 bit[4] gp34 bit[5] gp35 bit[6] gp36 bit[7] gp37 the pme wake status register is not affected by vcc por, soft reset or hard reset. writing a ?1? to bit[7:0] will cl ear it. writing a ?0? to any bit in pme wake status register has no effect.
134 name/default register offset description pme_en1 default = 0x00 on vtr por 05 (r/w) pme wake enable register 1 this register is used to enable individual lpc47n227 pme wake sources onto the nio_pme wake bus. when the pme wake enable register bit for a wake source is active (?1?), if the source asserts a wake event so that the associated status bit is ?1? and the pme_en bit is ?1?, the source will assert the nio_pme signal. when the pme wake enable register bit for a wake source is inactive (?0?), the pme wake status register will indicate the state of t he wake source but will not assert the nio_pme signal. bit[0] gp10 bit[1] gp11 bit[2] gp12 bit[3] gp13 bit[4] gp14 bit[5] gp15 bit[6] gp16 bit[7] gp17 the pme wake enable register is not affected by vcc por, soft reset or hard reset. pme_en2 default = 0x00 on vtr por 06 (r/w) pme wake enable register 2 this register is used to enable individual lpc47n227 pme wake sources onto the nio_pme wake bus. when the pme wake enable register bit for a wake source is active (?1?), if the source asserts a wake event so that the associated status bit is ?1? and the pme_en bit is ?1?, the source will assert the nio_pme signal. when the pme wake enable register bit for a wake source is inactive (?0?), the pme wake status register will indicate the state of t he wake source but will not assert the nio_pme signal. bit[0] ri1 bit[1] ri2 bit[2] gp20 bit[3] gp21 bit[4] gp22 bit[5] gp23 bit[6] gp24 bit[7] reserved the pme wake enable register is not affected by vcc por, soft reset or hard reset.
135 name/default register offset description pme_en3 default = 0x00 on vtr por 07 (r/w) pme wake enable register 3 this register is used to enable individual lpc47n227 pme wake sources onto the nio_pme wake bus. when the pme wake enable register bit for a wake source is active (?1?), if the source asserts a wake event so that the associated status bit is ?1? and the pme_en bit is ?1?, the source will assert the nio_pme signal. when the pme wake enable register bit for a wake source is inactive (?0?), the pme wake status register will indicate the state of t he wake source but will not assert the nio_pme signal. bit[0] gp30 bit[1] gp31 bit[2] gp32 bit[3] gp33 bit[4] gp34 bit[5] gp35 bit[6] gp36 bit[7] gp37 the pme wake enable register is not affected by vcc por, soft reset or hard reset. smi_sts1 default = 0x00 on vtr por 08 (r/w) smi status register 1 this register is used to read the status of the smi inputs. the following bits are cleared on a write of ?1?. bit[0] gp10 bit[1] gp11 bit[2] gp12 bit[3] gp13 bit[4] gp14 bit[5] gp15 bit[6] gp16 bit[7] gp17 smi_sts2 default = 0x01 on vtr por bit 0 is set to ?1? on vcc por, vtr por and hard reset 09 (r/w) smi status register 2 this register is used to read the status of the smi inputs. the bits[3:0] must be cleared at their source. bits[5:4] are cleared on a write of ?1?. bit[0] pint. the parallel port interrupt defaults to ?1? when the parallel port activate bit is cleared. when the parallel port is activated, pint follows the nack input. bit[1] u2int bit[2] u1int bit[3] fint bit[4] gp23 bit[5] gp24 bit[7:6] reserved
136 name/default register offset description smi_en1 default = 0x00 on vtr por 0a (r/w) smi enable register 1 this register is used to enab le the different interrupt sources onto the internal group nsmi signal. 1=enable 0=disable bit[0] gp10 bit[1] gp11 bit[2] gp12 bit[3] gp13 bit[4] gp14 bit[5] gp15 bit[6] gp16 bit[7] gp17 smi_en2 default = 0x00 on vtr por 0b (r/w) smi enable register 2 this register is used to enab le the different interrupt sources onto the internal group nsmi signal, and the internal group nsmi signal onto the nio_smi gpi/o pin or the serial irq stream on irq2. 1=enable 0=disable bit[0] en_pint bit[1] en_u2int bit[2] en_u1int bit[3] en_fint bit[4] gp23 bit[5] gp24 bit[6] en_smi_s (enable group nsmi signal onto serial irq2) bit[7] en_smi (enable group nsmi signal onto nio_smi pin) gp1 default = 0x00 on vtr por 0c r/w general purpose i/o data register 1 bit[0]gp10 bit[1]gp11 bit[2]gp12 bit[3]gp13 bit[4]gp14 bit[5]gp15 bit[6]gp16 bit[7]gp17 gp2 default = 0x00 on vtr por 0d r/w general purpose i/o data register 2 bit[0]gp20 bit[1]gp21 bit[2]gp22 bit[3]gp23 bit[4]gp24 bit[7:5]reserved
137 name/default register offset description gp3 default = 0x00 on vtr por 0e r/w general purpose i/o data register 3 bit[0]gp30 bit[1]gp31 bit[2]gp32 bit[3]gp33 bit[4]gp34 bit[5]gp35 bit[6]gp36 bit[7]gp37 gp4 default = 0x00 on vtr por 0f r/w general purpose i/o data register 4 bit[0]gp40 bit[1]gp41 bit[2]gp42 bit[3]gp43 bit[4]gp44 bit[5]gp45 bit[6]gp46 bit[7]gp47 note: reserved bits return 0 on read.
138 configuration the configuration of t he lpc47n227 is programmed through hardw are selectable configuration access ports that appear when the chip is placed into the confi guration state. the lpc47n227 logical device blocks, if enabled, will operate normally in the configur ation state. configuration access ports the configuration access port s are the config port, the i ndex port, and the data port (table 54). the base address of these registers is controlled by the gp 11/sysopt pin and by the configuration port base addr ess registers cr12 and cr13. to determine the conf iguration base address at power-up, the state of the gp11/sysopt pin is latched by the falling edge of a hardware reset. if the latched state is a 0, the base address of t he configuration access ports is located at address 0x02e; if the latched state is a 1, the base address is loca ted at address 0x04e. the base address is relocatable via cr12 and cr13. table 54 ? configuration access ports port name sysopt = 0 sysopt = 1 type config port 0x02e 0x04e write index port 0x02e 0x04e read/write 1,2 data port index port + 1 read/write 1 note 1 : the index and data ports are active only when the lpc47n227 is in the configuration state. note 2 : the index port is only readable in the configur ation state. configuration state the configuration register s are used to select programmable chip options. the lpc47n227 operates in two possible states: the run state and t he configuration state. after power up by default the chip is in the run state. to program the configuration regi sters, the configur ation state must be explicitly enabled. programming the configurat ion registers typically follows this sequence: 1. enter the conf iguration state, 2. program the confi guration register(s), 3. exit the conf iguration state. entering the conf iguration state to enter the configurat ion state write the conf iguration access key to the config port. the configuration access key is one byte of 55h data. the lpc47n227 will automatically activate the configuration access ports following this procedure. configuration register programming the lpc47n227 contains configur ation registers cr00-cr39. after the lpc47n227 enters the configuration state, configuration registers can be programmed by first writi ng the register index number (00 - 39h) to the configuration select register (csr) through t he index port and then writing or reading the configuration register contents through the data port. confi guration register access remains enabled until the configurati on state is exp licitly exited.
139 exiting the conf iguration state to exit the configurati on state, write one byte of aah data to the config port. the lpc47n227 will automatically deactivate the conf iguration access ports following th is procedure, at which point configuration register access c annot occur until the conf iguration state is ex plicitly re-enabled. programming example the following is a configuration register programming example wri tten in intel 8086 assembly language. ;----------------------------. ; enter configuration state | ;----------------------------' mov dx,02eh ;sysopt = 0 mov ax,055h out dx,al ;----------------------------. ; configure register cr0-crx | ;----------------------------' mov dx,02eh mov al,00h out dx,al ;point to cr0 mov dx,02fh mov al,3fh out dx,al ;update cr0 ; mov dx,02eh mov al,01h out dx,al ;point to cr1 mov dx,02fh mov al,9fh out dx,al ;update cr1 ; ; repeat for all crx registers ; ;-----------------------------. ; exit configuration state | ;-----------------------------' mov dx,02eh mov ax,aah out dx,al configuration select register (csr) the configuration select regist er can only be accessed when the lp c47n227 is in the configuration state. the csr is located at the index port address and must be initialized with configuration register index before t he register can be accessed using the data port.
140 configuration registers summary the configuration registers are se t to their default values at power up (table 55) and are reset as indicated in table 55 and the regi ster descriptions that follow. table 55 ? configuration registers summary register index type hard reset 1 vcc por vtr por register cr00 r/w - 0x28 - fdc power/valid config cycle cr01 r/w bit[7]=1 0x9c - pp power/mode/cr lock cr02 r/w bit[7]=0 0x08 - uart 1,2 power cr03 r/w - 0x70 - fdc miscellaneous cr04 r/w - 0x00 - pp and uart miscellaneous cr05 r/w - 0x00 - fdc setup cr06 r/w - 0xff - drive type id cr07 r/w bit[7:4]=0 0x00 - auto power mgt/boot drive select cr08 r/w - 0x00 - reserved cr09 r/w - 0x00 - test 4 cr0a r/w bit[7:6]=0 0x00 - ecp fifo threshold/ir mux cr0b r/w - 0x00 - drive rate cr0c r/w 0x02 0x02 - uart mode cr0d r - 0x5a - device id cr0e r - revision - revision id cr0f r/w - 0x00 - test 1 cr10 r/w - 0x00 - test 2 cr11 r/w - 0x80 - test 3 cr12 r/w sysopt=0:0x2e sysopt=1:0x4e - configuration base address 0 cr13 r/w sysopt=0:0x00 sysopt=1:0x00 - configuration base address 1 cr14 r - - - dsr shadow cr15 r - - - uart1 fcr shadow cr16 r - - - uart2 fcr shadow cr17 r/w - 0x03 - force fdd status change cr18 r - 0x00 - reserved cr19 r - 0x00 - reserved cr1a r - 0x00 - reserved cr1b r - 0x00 - reserved cr1c r - 0x00 - reserved cr1d r - 0x00 - reserved cr1e r - 0x00 - reserved cr1f r/w - 0x00 - drive type cr20 r/w - 0x3c - fdc base address cr21 r/w - 0x00 - fdc on pp/epp timeout select cr22 r/w - 0x00 - ecp software select cr23 r/w - 0x00 - parallel port base address cr24 r/w - 0x00 - uart1 base address cr25 r/w - 0x00 - uart2 base address
141 register index type hard reset 1 vcc por vtr por register cr26 r/w - 0x00 - fdc and pp dma select cr27 r/w - 0x00 - fdc and pp irq select cr28 r/w - 0x00 - uart irq select cr29 r/w - 0x80 - irqin1/hpmode/sirq_clkrun_ en cr2a r/w - 0x00 - irqin2 cr2b r/w - 0x00 - sce (fir) base address cr2c r/w - 0x00 - sce (fir) dma select cr2d r/w - 0x03 - ir half duplex timeout cr2e r/w - 0x00 - software select a cr2f r/w - 0x00 - software select b cr30 r/w - 0x00 - runtime register block address cr31 r/w - - 0x00 gpio direction register 1 cr32 r/w - - 0x00 gpio polarity register 1 cr33 r/w - - 0x00 gpio direction register 2 cr34 r/w - - 0x00 gpio polarity register 2 cr35 r/w - - 0x00 gpio direction register 3 cr36 r/w - - 0x00 gpio polarity register 3 cr37 r/w - - 0x00 gpio direction register 4 cr38 r/w - - 0x00 gpio polarity register 4 cr39 r/w - - 0x80 gpio output type register note: the bits that control the direction, polarity and output buffer type of each gpio also affect the alternate function on the gpio. note 1: hard reset: npci_reset pin asserted.
142 configuration registers description cr00 cr00 can only be accessed in the configuration st ate and after the csr has been initialized to 00h. table 56 ? cr00 fdc power/valid configuration cycle type: r/w default: 0x28 on vcc por bit no. bit name description 0-2 reserved read only. a read returns 0 3 fdc power 1 a high level on this bit, supplies power to the fdc (default). a low level on this bit puts the fdc in low power mode. 4,5,6 reserved read only. a read returns bit 5 as a 1 and bits 4 and 6 as a 0. 7 valid a high level on this software controlled bit can be used to indicate that a valid configuration cycle ha s occurred. the control software must take care to set this bit at the appropriate times. set to zero after power up. this bit has no e ffect on any other hardware in the chip. note 1 : power down bits disable the respective logi cal device and associated pins, however the power down bit does not disable the selected address range for the logical device. to disable the host address registers the logical device?s base address mu st be set below 100h. devices that are powered down but still reside at a valid i/o base address w ill participate in plug-and-play range checking.
143 cr01 cr01 can only be accessed in the configuration st ate and after the csr has been initialized to 01h. table 57 ? cr01 pp power/mode/cr lock type: r/w default: 0x9c on vcc por; bit[7] = 1 on hard reset bit no. bit name description 0,1 reserved read only. a read returns ?0?. 2 parallel port power 1 a high level on this bit, supplies powe r to the parallel port (default). a low level on this bit puts the parallel port in low power mode. 3 parallel port mode parallel port mode. a high level on this bit, sets the parallel port for printer mode (default). a low le vel on this bit enables the extended parallel port modes. refer to bits 0 and 1 of cr4 4 reserved read only. a read returns ?1?. 5,6 reserved read only. a read returns ?0?. 7 lock crx a high level on this bit enables the reading and writing of cr00 ? cr39 (default). a low level on this bit disables the reading and writing of cr00 ? cr39. note: once the lock crx bit is set to ?0?, this bit can only be set to ?1? by a hard reset or power-up reset. note 1 power down bits disable the respective logi cal device and associated pins, however the power down bit does not disable the selected address range for the logical device. to disable the host address registers the logical device?s base address mu st be set below 100h. devices that are powered down but still reside at a valid i/o base address w ill participate in plug-and-play range checking.
144 cr02 cr02 can only be accessed in the configuration st ate and after the csr has been initialized to 02h. table 58 ? cr02 uart 1 and 2 power type: r/w default: 0x08 on vcc por; bit[7] = 0 on hard reset bit no. bit name description 0-2 reserved read only. a read returns ?0?. 3 uart1 power down 1 a high level on this bit, allows norma l operation of the primary serial port (default). a low level on this bit places the primary serial port into power down mode. 4-6 reserved read only. a read returns ?0?. 7 uart2 power down 1 a high level on this bit, allows normal operation of the secondary serial port, including the sce/fir block (default). a low level on this bit places the secondary seri al port including the sce/fir block into power down mode. note 1 : power down bits disable the respective logi cal device and associated pins, however the power down bit does not disable the selected address range for the logical device. to disable the host address registers the logical device?s base address mu st be set below 100h. devices that are powered down but still reside at a valid i/o base address w ill participate in plug-and-play range checking.
145 cr03 cr03 can only be accessed in the configuration st ate and after the csr has been initialized to 03h. table 59 - cr03 fdc miscellaneous type: r/w default: 0x70 on vcc por bit no. bit name description 0 reserved read only. a read returns 0. bit 1 floppy mode ? refer to the description of the tape drive register (tdr) for more information on these modes. 0 normal floppy mode (default) 1 enhanced floppy mode 2 1 enhanced floppy mode 2 (os2) 2,3 reserved read only. a read returns 0. 4 drvden1 bit 4 pin drvden1 output 1 0 output programmed drvden1 value 1 force drvden1 output high (default) 5 mfm ident is used in conjunction with mfm to define the fdc interface mode. 6 ident ident 1 1 0 0 mfm 1 0 1 0 mode at mode (default) reserved ps/2 model 30 7 reserved read only. a read returns 0. note 1 : see note 2 in section cr05.
146 cr04 cr04 can only be accessed in the configuration st ate and after the csr has been initialized to 04h. table 60 ? cr04 pp and uart miscellaneous type: r/w default: 0x00 on vcc por bit no. bit name description bit 1 bit 0 if cr1 bit 3 is a low level then: 0 0 standard and bi-directional modes (spp) (default) 0 1 epp mode and spp 1 0 ecp mode 2 1,0 parallel port extended modes 1 1 ecp mode & epp mode 1,2 refer to parallel port floppy disk controller description. bit 3 bit 2 0 0 normal 0 1 ppfd1 1 0 ppfd2 2,3 parallel port fdc 1 1 reserved 4 midi 1 3 serial clock select port 1: a lo w level on this bit disables midi support (default). a high leve l on this bit enables midi support. 5 midi 2 3 serial clock select port 2: a lo w level on this bit disables midi support (default). a high leve l on this bit enables midi support. 6 epp type 0 = epp 1.9 (default) 1 = epp 1.7 7 reserved reserved - read as 0. note 1 : in this mode, epp can be selected through the ecr register of ecp as mode 100. note 2 : in these modes, 2 drives can be supported directly, 3 or 4 driv es must use external 4 drive support. spp can be selected through the ecr register of ecp as mode 000. note 3 : midi support: the musical instrumental digit al interface (midi) op erates at 31.25kbaud (+/-1%).
147 cr05 cr05 can only be accessed in the configuration st ate and after the csr has been initialized to 05h. table 61 ? cr05 floppy disk setup register type: r/w default: 0x00 on vcc por bit no. bit name description 0 1 fdc output type control (r/w) 0 = fdc outputs are open drain (default). 1 = fdc outputs are push-pull. 1 1,2 fdc output control (r/w) 0 = fdc outputs active (default). 1 = fdc outputs tri-state. 2 fdc dma mode 0 = burst mode is enabled fo r the fdc fifo execution phase data transfers (default). 1 = non-burst mode enabled. bit 4 bit 3 densel output 0 0 normal (default) 0 1 reserved 1 0 1 4,3 densel 1 1 0 5 swap drives 0,1 0= do not swap (default). 1= swap drives and motor sele ct 0 and 1 of the fdc on the parallel port. 6,7 reserved read only. a read returns 0. note 1 : bits cr05[1:0] do not affe ct the parallel port fdc. note 2 : in the lpc47n227, the behav ior of the drvden1 cont rol cr03.4 depends upon the fdc output control cr05.1 (table 62) . if the fdc output control is active drvden1 will behave as follows if cr03.4 is 0 the drvden1 out put pin assumes the value of the drvden1 function, if cr03.4 is 1 the drvden1 output pin stays high. if the fdc output control is inactive the drvden1 control will have no affect on the drvden1 output pin. table 62 ? drvden1 control fdc output control (cr05.1) drvden1 control (cr03.4) drvden1 (pin 2) description 0 0 1/0 normal drvden1 function 0 1 1 drvden1 forced high 1 x tristate all fdd output pins are tristated
148 cr06 cr06 can only be accessed in the configuration st ate and after the csr has been initialized to 06h. cr06 holds the floppy disk drive type ids for up to f our floppy disk drives (see table 6 ? drive type id in the floppy disk controller). table 63 ? cr06 drive type id register type: r/w default: 0xff on vcc por bit no. bit name description 0 id00 floppy disk drive 0 type id 0 1 id01 floppy disk drive 0 type id 1 2 id10 floppy disk drive 1 type id 0 3 id11 floppy disk drive 1 type id 1 4 id20 floppy disk drive 2 type id 0 5 id21 floppy disk drive 2 type id 1 6 id30 floppy disk drive 3 type id 0 7 id31 floppy disk drive 3 type id 1 cr07 cr07 can only be accessed in the configuration st ate and after the csr has been initialized to 07h. cr07 controls auto power managem ent and the floppy boot drive. table 64 ? cr07 auto power management and boot drive select type: r/w default: 0x00 on vcc por; bits[7:4] = 0000 on hard reset bit no. bit name description 0,1 floppy boot this bit is used to define the boot floppy. 0 = drive a (default) 1 = drive b 2,3 reserved read only. a read returns 0. 4 parallel port enable this bit controls the autopowe r down feature of the parallel port. the function is: 0 = auto powerdown disabled (default) 1 = auto powerdown enabled this bit is reset to the default st ate by por or a hardware reset. 5 uart 2 enable this bit controls the au topower down featur e of the uart2. the function is: 0 = auto powerdown disabled (default) 1 = auto powerdown enabled this bit is reset to the default st ate by por or a hardware reset. 6 uart 1 enable this bit controls the au topower down featur e of the uart1. the function is: 0 = auto powerdown disabled (default) 1 = auto powerdown enabled this bit is reset to the default st ate by por or a hardware reset.
149 auto power management and boot drive select type: r/w default: 0x00 on vcc por; bits[7:4] = 0000 on hard reset bit no. bit name description 7 floppy disk enable this bit controls the autopowe r down feature of the floppy disk. the function is: 0 = auto powerdown disabled (default) 1 = auto powerdown enabled this bit is reset to the default st ate by por or a hardware reset. cr08 register cr08 is reserved. the default val ue of this register after power up is 00h. cr09 cr09 can only be accessed in the configuration st ate and after the csr has been initialized to 09h. cr09 is a test control register and all bits must be treated as rese rved. note: all test modes are reserved for smsc use. activating test mode registers may pr oduce undesired results. table 65 ? cr09 test 4 type: r/w default: 0x00 on vcc por bit no. bit name description 0 test 24 1 test 25 2 test 26 3 test 27 4 test 28 5 test 29 6 test 30 7 test 31 reserved for smsc use cr0a cr0a can only be accessed in the c onfiguration state and after the cs r has been initialized to 0ah. cr0a defines the fifo threshold for the ecp mode par allel port. bits [5:4] are reserved. reserved bits cannot be written and return 0 when read. bits [7:6] are the ir output mux bits and are reset to the default state by a por and a hardware reset.
150 table 66 ? cr0a ecp fifo threshold/ir mux type: r/w default: 0x00 on vcc por; bits[7:6] = 00 on hard reset bit no. bit name description 0 thr0 ecp fifo threshold 0. 1 thr1 ecp fifo threshold 1. 2 thr2 ecp fifo threshold 2. 3 thr3 ecp fifo threshold 3. 4,5 reserved read only. a read returns 0. these bits are used to select ir output mux mode. bit7 bit6 mux mode 0 0 active device to com port (default). that is, depending on the mode of serial port 2, use pins 92, 94-100 for com signals or use rxd2 and txd2 (pins 95 and 96) for ir. when serial port 2 is inactive (power down bit = 0), then txd2 pin is low. the irtx2 pin is low. 0 1 active device to ir port. that is, use irrx2, irtx2 (pins 61, 62). when serial port 2 is inactive (power down bit = 0), then irtx2 pin is low. the txd2 pin is low. 1 0 reserved. 6,7 ir output mux 1 1 outputs inactive: txd2 and irtx2 are high-z, regardless of mode of uart2 and state of uart2 powerdown bit. cr0b cr0b can only be accessed in the c onfiguration state and after the cs r has been initialized to 0bh. cr0b indicates the drive rate table (table 68) used for each drive. refer to section cr1f for the drive type register.
151 table 67 ? cr0b drive rate type: r/w default: 0x00 on vcc por bit no. bit name description 0 fdd0 dtr0 floppy disk drive 0 drive rate table bit 0. 1 fdd0 dtr1 floppy disk drive 0 drive rate table bit 1. 2 fdd1 dtr0 floppy disk drive 1 drive rate table bit 0. 3 fdd1 dtr1 floppy disk drive 1 drive rate table bit 1. 4 fdd2 dtr0 floppy disk drive 2 drive rate table bit 0. 5 fdd2 dtr1 floppy disk drive 2 drive rate table bit 1. 6 fdd3 dtr0 floppy disk drive 3 drive rate table bit 0. 7 fdd3 dtr1 floppy disk drive 3 drive rate table bit 1. table 68 ? drive rate table (recommended) drt1 drt0 format 0 0 360k, 1.2m, 720k, 1.44m and 2.88m vertical format 0 1 3-mode drive 1 0 2 meg tape 1 1 reserved cr0c cr0c can only be accessed in the c onfiguration state and after the cs r has been initialized to 0ch. cr0c controls the operating m ode of the uart. this register is re set to the default state by a por or a hardware reset. table 69 ? cr0c uart mode type: r/w default: 0x02 on vcc por and hard reset bit no. bit name description 0 uart 2 rcv polarity 0 = rx input active high (default). 1 = rx input active low. 1 uart 2 xmit polarity 0 = tx output active high. 1 = tx output active low (default). 2 uart 2 duplex this bit is used to define the full/half duplex operation of uart 2. 1 = half duplex 0 = full duplex (default) 3, 4, 5 uart 2 mode uart 2 mode 5 4 3 0 0 0 standard com func tionality (default) 0 0 1 irda (hpsir) 0 1 0 amplitude shift keyed ir 0 1 1 reserved 1 x x reserved 6 uart 1 speed this bit enables the high speed mode of uart 1. 1 = high speed enabled 0 = standard (default)
152 uart mode type: r/w default: 0x02 on vcc por and hard reset bit no. bit name description 7 uart 2 speed this bit enables the high speed mode of uart 2. 1 = high speed enabled 0 = standard (default) cr0d cr0d can only be accessed in the c onfiguration state and after the cs r has been initialized to 0dh. this register is read only. cr0d contains the lpc47n227 device id. the default value of this register after power up is 5ah on vcc por. cr0e cr0e can only be accessed in the c onfiguration state and after the cs r has been initialized to 0eh. this register is read only. cr0e contains the cu rrent lpc47n227 chip revision level starting at 00h. cr0f cr0f can only be accessed in the c onfiguration state and after the cs r has been initialized to 0fh. cr0f is a test control register and all bits must be treated as rese rved. note: all test modes are reserved for smsc use. activating test mode registers may pr oduce undesired results. table 70 ? cr0f test 1 type: r/w default: 0x00 on vcc por bit no. bit name description 0 test 0 1 test 1 2 test 2 3 test 3 4 test 4 5 test 5 6 test 6 7 test 7 reserved for smsc use
153 cr10 cr10 can only be accessed in the configuration st ate and after the csr has been initialized to 10h. cr10 is a test control register and all bits must be treated as rese rved. note: all test modes are reserved for smsc use. activating test mode registers may pr oduce undesired results. table 71 ? cr10 test 2 type: r/w default: 0x00 on vcc por bit no. bit name description 0 test 8 1 test 9 2 test 10 3 test 11 4 test 12 5 test 13 6 test 14 7 test 15 reserved for smsc use cr11 cr11 can only be accessed in the configuration st ate and after the csr has been initialized to 11h. cr11 is a test control register and all bits must be treated as rese rved. note: all test modes are reserved for smsc use. activating test mode registers may pr oduce undesired results. table 72 ? cr11 test 3 type: r/w default: 0x80 on vcc por bit no. bit name description 0 test 16 1 test 17 2 test 18 3 test 19 4 test 20 5 test 21 6 test 22 7 test 23 reserved for smsc use cr12 - cr13 cr12 and cr13 are the lpc47n227 configuration po rts base address registers (table 73 and table 74). these registers are used to relocate t he configuration ports bas e address beyond the power-up defaults determined by the sysopt pin programming. cr12 contains the configur ation ports base address bits a[7:0]. cr13 contains the c onfiguration ports base address bits a[10:8]. the address bits a[15:11] must be ?00000? to access the configuration port. the configuration ports base address is reloca table on even-byte boundaries; i.e., a0 = ?0?. at power-up the configuration po rts base address is determined by t he sysopt pin programming. to relocate the configuration ports base address after pow er-up, first write the lower address bits of the
154 new base address to cr12 and then write t he upper address bits to cr13. note: writing cr13 changes the configurati on ports base address. table 73 ? cr12 configuration ports base address byte 0 (note) type: r/w default: 0x2e (sysopt=0) 0x4e (sysopt=1) on vcc por and hard reset bit no. bit name description 0 reserved read only. a read returns 0. 1 a1 2 a2 3 a3 4 a4 5 a5 6 a6 7 a7 configuration ports base address byte 0 for decoder. note: the configuration ports base address is relocatable on even-byte boundaries; i.e., a0 = ?0?. table 74 ? cr13 configuration ports base address byte 1 (note) type: r/w default: 0x00 (sysopt=0) 0x00 (sysopt=1) on vcc por and hard reset bit no. bit name description 0 a8 1 a9 2 a10 configuration ports base address byte 1 for decoder. 3-7 reserved read only. a read returns 0. note: writing cr13 changes the conf iguration ports base address.
155 cr14 cr14 can only be accessed in the configuration st ate and after the csr has been initialized to 14h. cr14 shadows the bits in the write- only fdc run-time dsr register. table 75 ? cr14 dsr shadow register type: r default: n/a bit no. bit name description 0,1 data rate select 0-1 these bits select the data rate of the floppy controller. 2-4 precomp 0-2 these three bits select th e value of write prec ompensation that will be applied to the wdata output signal. 5 reserved read only. a read returns 0. 6 pwrdown a logic "1" written to this bi t will put the floppy controller into manual low power mode. 7 softreset a logic "0" written to this bit resets the floppy disk controller. this bit is self clearing. cr15 cr15 can only be accessed in the configuration st ate and after the csr has been initialized to 15h. cr15 shadows the bits in the write- only uart1 run-time fcr register. table 76 - cr15 uart1 fcr shadow register type: r/w default: n/a bit no. bit name description 0 fifo enable setting this bit to a logic "1" enables both the xmit and rcvr fifos 1 rcvr fifo reset setting this bit to a logic "1" clears all bytes in the rcvr fifo and resets its counter logic to 0. this bit is self clearing. 2 xmit fifo reset setting this bit to a l ogic "1" clears all bytes in the xmit fifo and resets its counter logic to 0. this bit is self-clearing. 3 dma mode select writing to this bit has no effect on the operation of the uart. 4,5 reserved read only. a read returns 0. these bits are used to set the trigger level for the rcvr fifo interrupt. bit7 bit6 rcvr fifo trigger level (bytes) 0 0 1 0 1 4 1 0 8 6,7 rcvr trigger 1 1 14
156 cr16 cr16 can only be accessed in the configuration st ate and after the csr has been initialized to 16h. cr16 shadows the bits in the write-only uart2 r un-time fcr register. see cr15 for register description. cr17 cr17 can only be accessed in the configuration st ate and after the csr has been initialized to 17h. cr17 is the force fdd status change register. table 77 - cr17 force fdd status change register type: r/w default: 0x03 on vcc por bit no. bit name description 0,1 force dskchg 0-1 setting either of the force disk change bits active (1) forces the fdd ndskchg input active w hen the appropriate drive has been selected. force dskchg1 and force dskchg0 can be written to a 1 but are not clearable by software. force dskchg1 is cleared on (nstep and nds1), force dskchg0 is cleared on (nstep and nds0). note: the dsk chg bit in the floppy dir register, bit 7 = (nds0 and force dskchg0) or (nds1 and force dskchg1) or ndskchg. setting either of the force disk change bits active (1) forces the fdd ndskchg input active w hen the appropriate drive has been selected. bit[0] force change for fdc0 0=inactive 1=active bit[1] force change for fdc1 0=inactive 1=active 2 force wrtprt force wrtprt asserts the internal nwrtprt input to the controller when the force wrtprt bit is active (?1?) and a drive has been selected. the force wrtprt function applies to the nwrtprt pin in the fdd interface as well as the nwrtprt pin in the parallel port fdc. 3-7 reserved read only. a read returns 0. note: the controls in the force fdd status change regist er (cr17) apply to the fdd interface pins as well as to the parallel port fdc.
157 cr18 - cr1e cr18 - cr1e registers are reserved. reserved regi sters cannot be written and return 0 when read. the default value of these registers after power up is 00h on vcc por. cr1f cr1f can only be accessed in the c onfiguration state and after the cs r has been initialized to 1fh. cr1f indicates the floppy disk drive type for each of four floppy disk drives. the floppy disk drive type is used to map the three fdc densel, drate1 and drate0 outputs ont o two super i/o output pins drvden1 and drvden0 (table 79). table 78 ? cr1f drive type type: r/w default: 0x00 on vcc por bit no. bit name description 0 fdd0 dt1 drive type bit 1 for fdd 0. 1 fdd0 dt0 drive type bit 0 for fdd 0. 2 fdd1 dt1 drive type bit 1 for fdd 1. 3 fdd1 dt0 drive type bit 0 for fdd 1. 4 fdd2 dt1 drive type bit 1 for fdd 2. 5 fdd2 dt0 drive type bit 0 for fdd 2. 6 fdd3 dt1 drive type bit 1 for fdd 3. 7 fdd3 dt0 drive type bit 0 for fdd 3. table 79 ? drive type encoding drive type drvden0 drvden1 dt0 dt1 drive type description 0 0 densel drate0 4/2/1 mb 3.5? 2/1 mb 5.25? fdds 2/1.6/1 mb 3.5? (3-mode) 0 1 drate1 drate0 1 0 ndensel drate0 ps/2 1 1 drate0 drate1 cr20 cr20 can only be accessed in the configuration st ate and after the csr has been initialized to 20h. cr20 is used to select the base address of the floppy disk controller (fdc). the fdc base address can be set to 96 locations on 8 byte boundaries from 100h - 3f8h. to disable the fdc set adr9 and adr8 to zero. set cr20 .[1:0] to 00b when writing the fdc base address. fdc address decoding: address bits a[15:10] must be ?000000? to acce ss the fdc registers. a[3:0] are decoded as 0xxxb.
158 table 80 ? cr20 fdc base address type: r/w default: 0x3c on vcc por bit no. bit name description 0 reserved read only. a read returns 0. 1 reserved read only. a read returns 0. 2 adr4 3 adr5 4 adr6 5 adr7 6 adr8 7 adr9 fdc base address bits for decoder. cr21 cr21 can only be accessed in the configuration st ate and after the csr has been initialized to 21h. cr21 is the floppy on parallel port pin register. table 81 ? cr21 fdc on pp/epp timeout select type: r/w default: 0x00 on vcc por bit no. bit name description 0,1 fdc_pp fdc on parallel port pin bit1 bit0 description 0 0 bits in pp mode register control the fdc on the parallel port, the fdc_pp pin function is not used. 0 1 the fdc_pp pin controls the fdc on the pp as follows: (non-inverted polarity) when the pin is low, the parallel port pins are used for a floppy disk controller: drive 0 is on fdc pins, drive 1 is on parallel port pins. 1 0 the fdc_pp pin controls the fdc on the pp as follows: (non-inverted polarity) when the pin is low, the parallel port pins are used for a floppy disk controller: drive 0 is on parallel port pins and drive 1 is on parallel port pins. 1 1 reserved 2 timeout_select this bit selects the means of cl earing the timeout bit in the epp status register. if the timeout_select bit is cleared (?0?), the timeout bit is cleared on the tr ailing edge of the read of the epp status register (default). if the timeout_select bit is set (?1?), the timeout bit is cleared on a write of ?1? to the timeout bit. 3-7 reserved read only. a read returns 0. cr22
159 the ecp software select register cr22 contains the ecp irq select bits and the ecp dma select bits. cr22 is part of the ecp dma/irq software indi cators described in the ecp cnfgb register. cr22 is read/write. note: all of the ecp dma/irq so ftware indicators, including cr22, are software-only. writing these bits does not affect the ecp hardware dma or irq c hannels that are configured in cr26 and cr27. table 82 - cr22 ecp software select register type: r/w default: 0x00 on vcc por bit no. bit name description 2:0 ecp dma select ecp dma software indicator 5:3 ecp irq select ecp irq software indicator 6,7 reserved read only. a read returns 0. cr23 cr23 can only be accessed in the configuration st ate and after the csr has been initialized to 23h. cr23 is used to select the base addr ess of the parallel port. if epp is not enabled, the parallel port can be set to 192 locations on 4-byte boundaries from 100h - 3fch; if epp is enabled, the parallel port can be set to 96 locations on 8-byte boundaries from 100h - 3f8h. to disable the parallel port, set adr9 and adr8 to zero. parallel port address decoding: address bits a[15: 10] must be ?000000? to access the parallel port when in compatible, bi-directional, or epp modes. a10 is active when in ecp mode. table 83 - cr23 parallel port base address type: r/w default: 0x00 on vcc por bit no. bit name description 0 adr2 1 adr3 2 adr4 3 adr5 4 adr6 5 adr7 6 adr8 7 adr9 parallel port base addr ess bits for decoder. table 84 - parallel port addressing options epp enabled addressing (low bits) decode no a[1:0] = xxb yes a[2:0] = xxxb
160 cr24 cr24 can only be accessed in the configuration st ate and after the csr has been initialized to 24h. cr24 is used to select the base address of serial po rt 1 (uart1). the serial port can be set to 96 locations on 8-byte boundaries from 100h - 3f8h. to disable serial port 1, set adr9 and adr8 to zero. set cr24.0 to 0 when writing the uart1 base address. serial port 1 address decoding: address bits a[15: 10] must be ?000000? to access uart1 registers. a[2:0] are decoded as xxxb. table 85 - cr24 uart1 base address register type: r/w default: 0x00 on vcc por bit no. bit name description 0 reserved read only. a read returns 0. 1 adr3 2 adr4 3 adr5 4 adr6 5 adr7 6 adr8 7 adr9 serial port 1 base ad dress bits for decoder. cr25 cr25 can only be accessed in the configuration st ate and after the csr has been initialized to 25h. cr25 is used to select the base address of serial po rt 2 (uart2). serial port 2 can be set to 96 locations on 8-byte boundaries from 100h - 3f8h. to disable serial port 2, set adr9 and adr8 to zero. set cr25.0 to 0 when writing the uart2 base address. serial port 2 address decoding: address bits a[15: 10] must be ?000000? to access uart2 registers. a[2:0] are decoded as xxxb. table 86 - cr25 uart2 base address register type: r/w default: 0x00 on vcc por bit no. bit name description 0 reserved read only. a read returns 0. 1 adr3 2 adr4 3 adr5 4 adr6 5 adr7 6 adr8 7 adr9 serial port 2 base ad dress bits for decoder.
161 cr26 cr26 can only be accessed in the configuration st ate and after the csr has been initialized to 26h. cr26 is used to select the dma for the fdc (bits 4 - 7) and the parallel port (bits 0 - 3). any unselected dma request output (drq) is in tristate. table 87 - cr26 fdc and pp dma selection register type: r/w default: 0x00 on vcc por bit no. bit name description 3:0 pp dma select these bits are used to select dma for parallel port. 7:4 fdc dma select these bits are used to select dma for floppy disk controller. table 88 - dma selection bits[3:0] or bits[7:4] dma selected 0000 reserved 0001 dma1 0010 dma2 0011 dma3 0100 reserved .... .... ?. ?. 1110 reserved 1111 none cr27 cr27 can only be accessed in the configuration st ate and after the csr has been initialized to 27h. cr27 is used to select the irq for the fdc (bits 4 - 7) and the parallel port (bits 3 - 0). any unselected irq output (registers cr27 - cr29) is in tri-state. table 89 - cr27 fdc and pp irq selection register type: r/w default: 0x00 on vcc por bit no. bit name description 3:0 pp irq select these bits are used to select irq for parallel port. 7:4 fdc irq select these bits are used to select irq for floppy disk controller.
162 table 90 ? irq encoding bits[3:0] or bits[7:4] irq selected 0000 none 0001 irq_1 0010 irq_2 0011 irq_3 0100 irq_4 0101 irq_5 0110 irq_6 0111 irq_7 1000 irq_8 1001 irq_9 1010 irq_10 1011 irq_11 1100 irq_12 1101 irq_13 1110 irq_14 1111 irq_15 cr28 cr28 can only be accessed in the configuration st ate and after the csr has been initialized to 28h. cr28 is used to select the irq for serial port 1 (bits 7 - 4) and for serial port 2 (bits 3 - 0). refer to the irq encoding for cr27 (table 90) . any unselected irq output (register s cr27 - cr29) is in tristate. shared irqs are not suppor ted in the lpc47n227. table 91 ? cr28 uart interrupt selection type: r/w default: 0x00 on vcc por bit no. bit name description 3:0 uart2 irq select these bits are used to select ir q for serial port 2. see irq encoding for cr27 (table 90). 7:4 uart1 irq select these bits are used to select ir q for serial port 1. see irq encoding for cr27 (table 90).
163 table 92 ? uart interrupt operation uart1 uart2 irq pins uart1 out2 bit uart1 irq output state uart2 out2 bit uart2 irq output state uart1 pin state uart2 pin state 0 z 0 z z z 1 asserted 0 z 1 z 1 de-asserted 0 z 0 z 0 z 1 asserted z 1 0 z 1 de-asserted z 0 1 asserted 1 asserted 1 1 1 asserted 1 de-asserted 1 0 1 de-asserted 1 asserted 0 1 1 de-asserted 1 de-asserted 0 0 it is the responsibility of the software to ensure that two irq?s are not set to the same irq number. potential damage to chip ma y result. note: z = don?t care. cr29 cr29 can only be accessed in the configuration st ate and after the csr has been initialized to 29h. cr29 controls the hpmode bit and is used to select the irq mapping (bits 0 - 3) for the irqin1 pin. refer to irq encoding for cr27 (table 90) . any unselected irq output (r egisters cr27 - cr29) is in tristate. table 93 ? cr29 irqin1/hpmode/sirq_clkrun_en type: r/w default: 0x80 on vcc por bit no. bit name description 0-3 irqin1 selects the irq for irqin1. see figure 2 ? infrared interface block diagram 0 select irmode (default) 4 hpmode 1 select irrx3 5 reserved not writeable, reads return ?0? 7 sirq_clkrun_e n serial irq and clkrun enable bit. 0 = disable 1 = enable (default) cr2a cr2a can only be accessed in the c onfiguration state and after the cs r has been initialized to 2ah. cr2a is used to select the irq mapping (bits 0 - 3) for the irqin2 pin. refer to irq encoding for cr27 (table 90) . any unselected irq output (registers cr27 - cr29) is in tristate. table 94 ? cr2a irqin2 type: r/w default: 0x00 on vcc por bit no. bit name description 3:0 irqin2 selects the irq for irqin2. 7:4 reserved read only. a read returns 0.
164 cr2b cr2b can only be accessed in the c onfiguration state and after the cs r has been initialized to 2bh. cr2b is used to set the sce (fir) base address adr[10:3]. the sce base address can be set to 224 locations on 8-byte boundaries from 100h - 7f8h. to disable the sce, set adr10, adr9 and adr8 to zero. sce address decoding: address bits a[15:11] must be ?00000? to acce ss sce registers. a[2:0] are decoded as xxxb. table 95 - cr2b sce (fir) base address register type: r/w default: 0x00 on vcc por bit no. bit name description 0 adr3 1 adr4 2 adr5 3 adr6 4 adr7 5 adr8 6 adr9 7 adr10 fir base address bits for decoder. cr2c cr2c can only be accessed in the c onfiguration state and after the cs r has been initialized to 2ch. bits d[3:0] of this register are used to select the dma for the sce (f ir). bits d[7:4] are reserved. reserved bits cannot be written and return 0 when read. any unselected dma r equest output (drq) is in tristate. table 96 - cr2c sce (fir) dma select register type: r/w default: 0x00 on vcc por bit no. bit name description bit3 bit2 bit1 bit0 dma selected 0 0 0 0 reserved 0 0 0 1 dma1 0 0 1 0 dma2 0 0 1 1 dma3 0 1 0 0 reserved . . . . . . . . . . 1 1 1 0 reserved 3:0 dma select 1 1 1 1 none 7:4 reserved read only. a read returns 0.
165 cr2d cr2d can only be accessed in the c onfiguration state and after the cs r has been initialized to 2dh. cr2d is used to set the ir half duplex turnaround de lay time for the ir port. this value is 0 to 25.5msec in 100sec increments. the ircc v2.0 block includes an 8 bit ir half duplex time-out register in sce register block 5, address 1 that interacts with c onfiguration register cr2 d. these two regist ers behave like the other ircc legacy controls where either source uniformly updates the value of both registers when either register is explicitly written or following a device-level por. ircc software resets do not affect these registers. the ir half duplex time-out is programmable from 0 to 25.5ms in 100 s increments, as follows: ir half duplex time-out = (cr2d) x 100 s table 97 ? cr2d ir half duplex timeout type: r/w default: 0x03 on vcc por bit no. bit name description 0-7 ir half duplex time out these bits are used to set the ir half duplex turnaround delay time for the ir port. this value is 0 to 25.5msec in 100sec increments. cr2e cr2e can only be accessed in the c onfiguration state and after the cs r has been initialized to 2eh. cr2e is directly connected to sce register blo ck three, address 0x05 in the ircc v2.0 block. table 98 ? cr2e software select a type: r/w default: 0x00 on vcc por bit no. bit name description 0-7 software select a these bits are directly connected to sce register block three, address 0x05 in the ircc v2.0 block. cr2f cr2f can only be accessed in the c onfiguration state and after the cs r has been initialized to 2fh. cr2f is directly connected to sce register blo ck three, address 0x06 in the ircc v2.0 block. table 99 ? cr2f software select b type: r/w default: 0x00 on vcc por bit no. bit name description 0-7 software select b these bits are directly connected to sce register block three, address 0x06 in the ircc v2.0 block. cr30 cr30 can only be accessed in the configuration st ate and after the csr has been initialized to 30h. cr30 is used to set the runtime register block bas e address adr[11:4]. the runtime register block
166 base address can be set to 240 locations on 16-by te boundaries from 100h ? ff0h. to disable runtime registers block, set adr11 ? adr8 to zero. sce address decoding: address bits a[15:12] must be ?0000? to access runtime register block registers. a[3:0] are decoded as xxxxb. table 100 ? cr30 runtime registers block base address type: r/w default: 0x00 on vcc por bit no. bit name description 0 adr4 1 adr5 2 adr6 3 adr7 4 adr8 5 adr9 6 adr10 7 adr11 the bits in this register are us ed to program the location of the runtime register block base address. cr31 cr31 can only be accessed in the configuration st ate and after the csr has been initialized to 31h. cr31 is gpio direction register 1 and is used to select the direction of gp10-gp17 pins. table 101 ? cr31 gpio direction register 1 type: r/w default: 0x00 on vtr por bit no. bit name description 0 gp10 1 gp11 2 gp12 3 gp13 4 gp14 5 gp15 6 gp16 7 gp17 the bits in this register are us ed to select the direction of the gp10-gp17 pins. 0=input 1=output
167 cr32 cr32 can only be accessed in the configuration st ate and after the csr has been initialized to 32h. cr32 is gpio polarity register 1 and is used to select the polarity of gp10-gp17 pins. table 102 ? cr32 gpio polarity register 1 type: r/w default: 0x00 on vtr por bit no. bit name description 0 gp10 1 gp11 2 gp12 3 gp13 4 gp14 5 gp15 6 gp16 7 gp17 the bits in this register are used to select the polarity of the gp10- gp17 pins. 0=non-inverted 1=inverted cr33 cr33 can only be accessed in the configuration st ate and after the csr has been initialized to 33h. cr33 is gpio direction register 2. it is used to select the direction of gp20-gp24 pins, and select alternate function on gp23 and gp12 pins. table 103 ? cr33 gpio direction register 2 type: r/w default: 0x00 on vtr por bit no. bit name description 0 gp20 1 gp21 2 gp22 3 gp23 4 gp24 these bits are used to select the direction of the gp20-gp24. 0=input 1=output 5 reserved read only. a read returns 0. 6 gp23 alternate function select 0=gpio 1=fdc_pp (when this function is selected, the pin must be selected as an input. polarity is controlled by the polarity bit. if enabled for pme or smi, the inte rrupt is generated on either edge.) 7 gp12 alternate. function select 0=gpio 1=nio_smi note: selecting the nio_smi function with gp12 configured with non-inverted polarity will give an active low output signal. the output type can be programm ed for open drain via cr39.
168 cr34 cr35 can only be accessed in the configuration st ate and after the csr has been initialized to 34h. cr34 is gpio polarity register 2. it is used to select the polarity of gp20-gp24 and io_pme pins, and select alternate function on gp13 and gp14 pins. table 104 ? cr34 gpio polarity register 2 type: r/w default: 0x00 on vtr por bit no. bit name description 0 gp20 1 gp21 2 gp22 3 gp23 4 gp24 these bits are used to select t he polarity of the gp20-gp24 pins. 0=non-inverted 1=inverted 5 nio_pme polarity select this bit is used to select t he polarity of the nio_pme pin. 0=non-inverted 1=inverted note: configuring this pin function with non-inverted polarity will give an active low output signal. the output type can be either open drain or push-pull. (see cr39). 6 gp13 alternate function select 0=gpio 1=irqin1 7 gp14 alternate function select 0=gpio 1=irqin2 cr35 cr35 can only be accessed in the configuration st ate and after the csr has been initialized to 35h. cr35 is gpio direction register 3 and is used to select the direction of gp30-gp37 pins. table 105 ? cr35 gpio direction register 3 type: r/w default: 0x00 on vtr por bit no. bit name description 0 gp30 1 gp31 2 gp32 3 gp33 4 gp34 5 gp35 6 gp36 7 gp37 the bits in this register are us ed to select the direction of the gp30-gp37 pins. 0=input 1=output
169 cr36 cr36 can only be accessed in the configuration st ate and after the csr has been initialized to 36h. cr36 is gpio polarity register 3 and is used to select the polarity of gp30-gp37 pins. table 106 ? cr36 gpio polarity register 3 type: r/w default: 0x00 on vtr por bit no. bit name description 0 gp30 1 gp31 2 gp32 3 gp33 4 gp34 5 gp35 6 gp36 7 gp37 the bits in this register are used to select the polarity of the gp30- gp37 pins. 0=non-inverted 1=inverted cr37 cr37 can only be accessed in the configuration st ate and after the csr has been initialized to 37h. cr37 is gpio direction register 4 and is used to select the direction of gp40-gp47 pins. table 107 ? cr37 gpio direction register 4 type: r/w default: 0x00 on vtr por bit no. bit name description 0 gp40 1 gp41 2 gp42 3 gp43 4 gp44 5 gp45 6 gp46 7 gp47 the bits in this register are us ed to select the direction of the gp40-gp47 pins. 0=input 1=output
170 cr38 cr38 can only be accessed in the configuration st ate and after the csr has been initialized to 38h. cr38 is gpio polarity register 4 and is used to select the polarity of gp40-gp47 pins. table 108 ? cr38 gpio polarity register 4 type: r/w default: 0x80 on vtr por bit no. bit name description 0 gp40 1 gp41 2 gp42 3 gp43 4 gp44 5 gp45 6 gp46 7 gp47 the bits in this register are used to select the polarity of the gp40- gp47 pins. 0=non-inverted 1=inverted cr39 cr39 can only be accessed in the configuration st ate and after the csr has been initialized to 39h. cr39 is gpio output register and is used to select the output buffe r of gp12-gp17, gp20 and nio_pme pins. table 109 ? cr39 gpio output register type: r/w default: 0x00 on vtr por bit no. bit name description 0 gp12 1 gp13 2 gp14 3 gp15 4 gp16 5 gp17 6 gp20 7 nio_pme the bits in this register are used to select the output buffer type of the gp12-gp17, gp20 and nio_pme pins. 0=push-pull 1=open drain
171 logical device base i/o address and range table 110 ? i/o base address configuration register description logical device register index base i/o range (note 1) fixed base offsets fdc 0x20 [0x0100:0x03f8] on 8-byte boundaries +0 : sra +1 : srb +2 : dor +3 : tdr +4 : msr/dsr +5 : fifo +7 : dir/ccr [0x0100:0x03fc] on 4-byte boundaries (epp not supported) or [0x0100:0x03f8] on 8-byte boundaries +0 : data/ecpafifo +1 : status +2 : control +400h : cfifo/ecpdfifo/tfifo/cnfga +401h : cnfgb +402h : ecr parallel port 0x23 (all modes supported, epp is only available when the base address is on an 8-byte boundary) +3 : epp address +4 : epp data 0 +5 : epp data 1 +6 : epp data 2 +7 : epp data 3 serial port 1 0x24 [0x0100:0x03f8] on 8 byte boundaries +0 : rb/tb/lsb div +1 : ier/msb div +2 : iir/fcr +3 : lcr +4 : mcr +5 : lsr +6 : msr +7 : scr 0x25 [0x0100:0x03f8] on 8-byte boundaries +0 : rb/tb/lsb div +1 : ier/msb div +2 : iir/fcr +3 : lcr +4 : mcr +5 : lsr +6 : msr +7 : scr serial port 2 0x2b (fir/cir) [0x100:0x07f8] on 8-byte boundaries +0 : dr/scea/circ/idh/(irdacr/bofh) +1 : intid/sceb/circr/idl/bofl +2 : ier/fifot/cirbr/cid/bwcl +3 : lsr/lsa/vern/(bwch/tdsh) +4 : lca/(irql/dmac)/tdsl +5 : lcb/rdsh +6 : bs/rdsl +7 : mcr
172 logical device register index base i/o range (note 1) fixed base offsets runtime register block 0x30 [0x0100:0x0ff0] on 16-byte boundaries +00 : pme_sts . . . +0f : gp4 (see table 52 in the runtime registers section for full list) config. port 0x12, 0x13 (note 2) [0x0100:0x07fe] on 2-byte boundaries see configuration registers in table 55. they are accessed through the index and data ports located at the configuration port address and the c onfiguration port address +1 respectively. note 2: the configuration port is at either 0x02e or 0x04e (f or sysopt=0 or sysopt=1) at power up and can be relocated via cr12 and cr13. note a. logical device irq and dma operation 1. irq and dma enable and disable: any time t he irq or dma channel for a logical block is disabled by a register bit in that logical block, the ir q and/or dma channel is disabled. this is in addition to the irq and dma channel disabled by the configurat ion registers (active bit or address not valid). a. fdc: for the following cases, the irq and dma channel used by the fdc are disabled. digital output register (base+ 2) bit d3 (dmaen) set to "0". the fdc is in power down (disabled). b. serial ports: modem control register (mcr) bit d2 (out2) - when out2 is a logic "0", the serial port interruptis disabled. disabling dma enable bit, disables dma for ua rt2. refer to the ircc specification. c. parallel port: i. spp and epp modes: control port (base+2) bit d4 (irqe) set to "0", irq is disabled. ii. ecp mode: (1) (dma) dmaen from ecr register. see table below. (2) irq - see table below. mode (from ecr register) irq controlled by dma controlled by 000 printer irqe dmaen 001 spp irqe dmaen 010 fifo (on) dmaen 011 ecp (on) dmaen 100 epp irqe dmaen 101 res irqe dmaen 110 test (on) dmaen
173 mode (from ecr register) irq controlled by dma controlled by 111 config irqe dmaen operational description maximum guaranteed ratings operating temper ature ra nge.................................................................................................... .0 o c to +70 o c storage temperat ure r ange ..................................................................................................... - 55 o to +150 o c lead temperature range ........................................................................... refer to jedec spec. j-std-020 positive voltage on any pin, with respect to gr ound ......................................................................... v cc +0.3v negative voltage on any pin, with respec t to ground ............................................................................ ... -0.3v maximum v cc ............................................................................................................................... ............... +7v note: stresses above those list ed above could cause permanent damage to the device. this is a stress rating only and functional operat ion of the device at any other condition above those indicated in the operation sections of this specification is not implied. note: when powering this device from laboratory or system power supplies, it is important that the absolute maximum ratings not be exceeded or device fa ilure can result. some power supplies exhibit voltage spikes on their outputs when t he ac power is switched on or o ff. in addition, voltage transients on the ac power line may appear on the dc output. if this possibility exists, it is suggested that a clamp circuit be used. dc electrical characteristics (t a = 0 0 c ? 70 0 c, v cc = +3.3 v 10%) parameter symbol min typ max units comments i type input buffer low input level high input level v ili v ihi 2.0 0.8 v v ttl levels is type input buffer low input level high input level schmitt trigger hysteresis v ilis v ihis v hys 2.2 100 0.8 v v mv schmitt trigger schmitt trigger input leakage, i and is buffers low input leakage high input leakage i il i ih -10 -10 +10 +10 a a v in = 0 v in = v cc
174 parameter symbol min typ max units comments o6 type buffer low output level high output level v ol v oh 2.4 0.4 v v i ol = 6ma i oh = -3ma io8 type buffer low output level high output level input leakage current v ol v oh i leak 2.4 -10 0.4 +10 v v a i ol = 8ma i oh = -4ma v in = 0 to v cc (note 1) o8 type buffer low output level high output level v ol v oh 2.4 0.4 v v i ol = 8ma i oh = -4ma o12 type buffer low output level high output level v ol v oh 2.4 0.4 v v i ol = 12ma i oh = -6ma io12 type buffer low output level high output level input leakage current v ol v oh i leak 2.4 -10 0.4 +10 v v a i ol = 12ma i oh = -6ma v in = 0 to v cc (note 1) od12 type buffer low output level input leakage current v ol i leak -10 0.4 +10 v a i ol = 12ma v in = 0 to v cc od14 type buffer low output level input leakage current v ol i leak -10 0.4 +10 v a i ol = 14ma v in = 0 to v cc
175 parameter symbol min typ max units comments op14 type buffer low output level high output level input leakage current v ol v oh i leak 2.4 -10 0.4 +10 v v a i ol = 14ma i oh = -14ma v in = 0 to v cc (note 1) iop14 type buffer low output level high output level input leakage current v ol v oh i leak 2.4 -10 0.4 +10 v v a i ol = 14ma i oh = -14ma v in = 0 to v cc (note 1) backdrive protect/chiprotect (all pins excluding lad[3:0], nldrq, nlpcpd, nlframe) i il 10 a v cc = 0v v in = 5.5v max 5v tolerant pins (all pins excluding lad[3:0], nldrq, nlpcpd, nlframe) inputs and outputs in high impedance state i il 10 a v cc = 3.3v v in = 5.5v max lpc bus pins (lad[3:0], nldrq, nlpcpd, nlframe) i il 10 a v cc = 3.3v v in = 3.6v max v cc supply current active i cci 25 3 ma all outputs open, all inputs in a fixed state (i.e., 0v or 3.3v) trickle supply voltage v tr v cc min -.5v 5 v cc max v v cc must not be greater than .5v above v tr v tr supply current active i tri 0.1 3,4 ma all outputs open, all inputs in a fixed state (i.e., 0v or 3.3v) note 1: all output leakage?s are meas ured with all pins in high impedance note 2: output leakage is measured with the low driving output off, either for a high level output or a high impedance state. note 3: contact smsc for the latest values. note 4: max i tri with v cc = 3.3v (nominal) is 0.1ma. max i tri with v cc = 0v (nominal) is 50 a. note 5: the minimum value given for v tr applies when v cc is active. when v cc is 0v, the minimum v tr is 0v.
176 capacitance t a = 25 0 c; fc = 1mhz; v cc = 3.3v 10% limits parameter symbol min typ max unit test condition clock input capacitance c in 20 pf input capacitance c in 10 pf output capacitance c out 20 pf all pins except pin under test tied to ac ground
177 timing diagrams for the timing diagrams shown, the follo wing capacitive loads are used on outputs. name capacitance total (pf) ser_irq 50 nlad[3:0] 50 nldrq 50 ndir 240 nstep 240 nds0-1 240 nwdata 240 pd[0:7] 240 nstrobe 240 nalf 240 slctin 240 txd1 50 txd2 50 nclkrun 50
178 t3 vcc all host a ccesses t2 t1 figure 6 - power-up timing name description min typ max units t1 vcc slew from 2.7v to 0v 300 s t2 vcc slew from 0v to 2.7v 100 s t3 all host accesses after powerup (note 1) 125 500 s note 1: internal write-protection per iod after vcc passes 2.7 volts on power-up
179 t1 t2 t2 clocki figure 7 - input clock timing name description min typ max units t1 clock cycle time for 14.318mhz 69.84 ns t2 clock high time/low time for 14.318mhz 20 35 ns t1 clock cycle time for 32khz 31.25 s t2 clock high time/low time for 32khz 16.53 s clock rise time/fall time (not shown) 5 ns t1 t3 t2 pci_clk t5 t4 figure 8 ? pci clock timing name description min typ max units t1 period 30 33.3 nsec t2 high time 12 nsec t3 low time 12 nsec t4 rise time 3 nsec t5 fall time 3 nsec t1 npci_reset figure 9 - reset timing name description min typ max units t1 npci_reset width 1 ms
180 t3 t2 t1 clk output delay tri-state output figure 10 ? output timing meas urement conditions, lpc signals name description min typ max units t1 clk to signal valid delay ? bused signals 2 11 ns t2 float to active delay 2 11 ns t3 active to float delay 28 ns inputs valid t2 t1 clk input figure 11 ? input timing measure ment conditions, lpc signals name description min typ max units t1 input set up time to clk ? bused signals 7 ns t2 input hold time from clk 0 ns
181 l1 l2 a ddress data tar sync=0110 l3 tar pci_clk nlframe nlad[3:0] note: l1=start; l2=cyctyp+dir; l3=sync of 0000 figure 12 ? i/o write l1 l2 a ddress tar sync=0110 l3 data tar pci_clk nlframe nlad[3:0] note: l1=start; l2=cyctyp+dir; l3=sync of 0000 figure 13 ? i/o read
182 start msb lsb a ct pci_clk nldrq figure 14 ? dma request assertion through nldrq start c+d chl size tar sync=0101 l1 data tar pci_clk nlframe nlad[3:0] note: l1=sync of 0000 figure 15 ? dma write (first byte) start c+d chl size data tar sync=0101 l1 tar pci_clk nlframe nlad[3:0] note: l1=sync of 0000 figure 16 ? dma read (first byte)
183 t3 t1 t2 t4 t5 t6 t7 t8 ndir nstep nds0-1 ninde x nrdata nwdata t9 figure 17 ? floppy disk drive timing (at mode only) name description min typ max units t1 ndir set up to step low 4 x* t2 nstep active time low 24 x* t3 ndir hold time after nstep 96 x* t4 nstep cycle time 132 x* t5 nds0-1 hold time from nstep low (note) 20 x* t6 nindex pulse width 2 x* t7 nrdata active time low 40 ns t8 nwdata write data width low .5 y* t9 nds0-1, setup time ndir low (note) 0 ns *x specifies one mclk period and y specifies one wclk period. mclk = 16 x data rate (at 500 kb/s mclk = 8 mhz) wclk = 2 x data rate (at 500 kb/s wclk = 1 mhz) note: the nds0-1 setup and hold times must be met by software.
184 t9 t8 t7 t6 t4 t5 t3 t2 t1 nwrite pd<7:0> ndatastb naddrstb nwait figure 18 ? epp 1.9 data or address write cycle name description min typ max units t1 nwait asserted to nwrite asserted (note 1) 60 185 ns t2 nwait asserted to nwrite change (note 1) 60 185 ns t3 nwait asserted to pdata invalid (note 1) 0 ns t4 pdata valid to command asserted 10 ns t5 nwrite to command asserted 5 35 ns t6 nwait asserted to command asserted (note 1) 60 210 ns t7 nwait deasserted to command deasserted (note 1) 60 190 ns t8 command asserted to nwait deasserted 0 10 s t9 command deasserted to nwait asserted 0 ns note 1: nwait must be filtered to compensate for ringing on the par allel bus cable. wait is considered to have settled after it does not transition for a minimum of 50 nsec.
185 t12 t11 t10 t9 t7 t8 t6 t5 t4 t3 t2 t1 nwrite pd<7:0> ndatastb naddrstb nwait figure 19 ? epp 1.9 data or address read cycle name description min typ max units t1 nwait asserted to nwrite deasserted 0 185 ns t2 nwait asserted to nwrite mo dified (notes 1,2) 60 190 ns t3 nwait asserted to pdata hi-z (note 1) 60 180 ns t4 command asserted to pdata valid 0 ns t5 command deasserted to pdata hi-z 0 ns t6 nwait asserted to pdata driven (note 1) 60 190 ns t7 pdata hi-z to command asserted 0 30 ns t8 nwrite deasserted to command 1 ns t9 nwait asserted to command asserted 0 195 ns t10 nwait deasserted to command deasserted (note 1) 60 180 ns t11 pdata valid to nwait deasserted 0 ns t12 pdata hi-z to nwait asserted 0 s note 1: nwait is considered to have settled afte r it does not transition for a minimum of 50 ns. note 2: when not executing a write cy cle, epp nwrite is inactive high.
186 t5 t4 t3 t2 t1 nwrite pd<7:0> ndatastb naddrstb nwait figure 20 ? epp 1.7 data or address write cycle name description min typ max units t1 command deasserted to nwrite change 0 40 ns t2 command deasserted to pdata invalid 50 ns t3 pdata valid to command asserted 10 35 ns t4 nwrite to command 5 35 ns t5 command deasserted to nwait deasserted 0 ns
187 t3 t2 t1 nwrite pd<7:0> ndatastb naddrstb nwait figure 21 ? epp 1.7 data or address read cycle name description min typ max units t1 command asserted to pdata valid 0 ns t2 command deasserted to pdata hi-z 0 ns t3 command deasserted to nwait deasserted 0 ns
188 ecp parallel port timing parallel port fifo (mode 101) the standard parallel port is run at or near the peak 500kbytes/sec allowed in the forward direc- tion using dma. the st ate machine does not examine nack and begins the next transfer based on busy. refer to figure 22. ecp parallel port timing the timing is designed to allow operation at approximately 2.0 mbytes/sec over a 15ft cable. if a shorter cable is used then the bandwidth will increase. forward-idle when the host has no data to send it keeps hostclk (nstrobe) high and the peripheral will leave periphclk (busy) low. forward data transfer phase the interface transfers data and commands from the host to the peripheral using an interlocked periphack and hostclk. the peripheral may indicate its desire to send data to the host by asserting nperiphrequest. the forward data transfer phase may be entered from the forward-idle phas e. while in the forward phase the peripheral may asynchronously assert the nperiphrequest (nfault) to request that the channel be reversed. when the peripheral is not busy it sets periphack (busy) low. the host then sets hostclk (nstrobe) low when it is prepared to send data. the data must be stable for the specified setup time prior to the falling edge of hostclk. the peripheral then sets periphack (busy) high to acknowledge the handshake. the host then sets hostclk (nstrobe) high. the peripheral then accepts the data and sets periphack (busy) low, completing the transfer. this sequence is shown in figure 23. the timing is designed to provide 3 cable round-trip times for data setup if data is driven simultaneously with hostclk (nstrobe). reverse-idle phase the peripheral has no data to send and keeps periphclk high. the host is idle and keeps hostack low. reverse data transfer phase the interface transfers data and commands from the peripheral to the host using an interlocked hostack and periphclk. the reverse data transfer phase may be en- tered from the reverse-idle phase. after the previous byte has beed accepted the host sets hostack (nalf) low. the peripheral then sets periphclk (nack) low when it has data to send. the data must be stable fo r the specified setup time prior to the falling edge of periphclk. when the host is ready to accept a byte it sets hostack (nalf) high to acknowledge the handshake. the peripheral then sets periphclk (nack) high. after the host has accepted the data it sets hostack (nalf) low, completing the transfer. this sequence is shown in figure 24.
189 output drivers to facilitate higher performance data transfer, the use of balanced cmos active drivers for critical signals (data, hostack, hostclk, periphack, periph clk) are used in ecp mode. because the use of active drivers can present compat ibility problems in compatible mode (the control signals, by tradition, are specified as open-collector), t he drivers are dynamically changed fr om open-collector to totem-pole. the timing for the dynamic driver change is spec ified in then ieee 1284 ex tended capabilities port protocol and isa interface standard, rev. 1.14, july 14, 1993, ava ilable from microsoft. the dynamic driver change must be impl emented properly to prevent glitching the outputs.
t3 t6 t1 t2 t5 t4 pd<0:7> nstrobe busy figure 22 ? parallel port fifo timing name description min typ max units t1 pdata valid to nstrobe active 600 ns t2 nstrobe active pulse width 600 ns t3 pdata hold from nstrobe inactive (note 1) 450 ns t4 nstrobe active to busy active 500 ns t5 busy inactive to nstrobe active 680 ns t6 busy inactive to pdata invalid (note 1) 80 ns note 1: the data is held until busy goes inactive or for time t3, whichever is longer. this only applies if another data transfer is pending. if no other data tr ansfer is pending, the dat a is held indefinitely.
191 t3 t4 t1 t2 t7 t8 t6 t5 t6 nalf pd<7:0> busy nstrobe figure 23 - ecp parallel port forward timing name description min typ max units t1 nalf valid to nstrobe asserted 0 60 ns t2 pdata valid to nstrobe asserted 0 60 ns t3 busy deasserted to nalf changed (notes 1,2) 80 180 ns t4 busy deasserted to pdata changed (notes 1,2) 80 180 ns t5 nstrobe asserted to busy asserted 0 ns t6 nstrobe deasserted to busy deasserted 0 ns t7 busy deasserted to nstrobe asserted (notes 1,2) 80 200 ns t8 busy asserted to nstrobe deasserted (note 2) 80 180 ns note 1: maximum value only applies if there is data in the fifo waiting to be written out. note 2: busy is not considered asserted or deasserted until it is stable for a minimum of 75 to 130 ns.
192 t2 t1 t5 t6 t4 t3 t4 pd<7:0> nack nalf figure 24 - ecp parallel port reverse timing name description min typ max units t1 pdata valid to nack asserted 0 ns t2 nalf deasserted to pdata changed 0 ns t3 nack asserted to nalf deasserted (notes 1,2) 80 200 ns t4 nack deasserted to nalf asserted (note 2) 80 200 ns t5 nalf asserted to nack asserted 0 ns t6 nalf deasserted to nack deasserted 0 ns note 1: maximum value only applies if there is room in the fifo and terminal count has not been received. ecp can stall by keeping nalf low. note 2: nack is not considered asserted or deasserted until it is stable for a minimum of 75 to 130 ns.
193 t1 t2 t2 t1 0 101 0 0 11011 data irrx n irrx t1 t1 t1 t1 t1 t1 t1 t2 t2 t2 t2 t2 t2 t2 pa rame ter min ty p m ax units 1. 4 1. 4 1. 4 1. 4 1. 4 1. 4 1. 4 2. 71 3. 69 5. 53 11.07 22.13 44.27 88.55 s s s s s s s s s s s s s s pulse w idt h at 1 15kba ud pul se wid th at 57. 6kba ud pul se wid th at 38. 4kba ud pul se wid th at 19. 2kba ud pu lse wi dt h a t 9. 6kba ud pu lse wi dt h a t 4. 8kba ud pu lse wi dt h a t 2. 4kba ud bit t ime at 1 15kba ud bit t ime at 57. 6kba ud bit t ime at 38. 4kba ud bit t ime at 19. 2kba ud bi t ti me a t 9. 6kba ud bi t ti me a t 4. 8kba ud bi t ti me a t 2. 4kba ud 1. 6 3. 22 4. 8 9. 7 19. 5 39 78 8. 68 17. 4 26 52 104 208 416 no te s: 1. recei ve pu lse det ect ion c ri te ria: a re ceived p ulse is consi dered d et ecte d if t he received pulse is a minimum of 1.41s. 2. ir rx : l5, crf 1 b it 0 = 1 nirrx: l5, crf1 bit 0 = 0 ( def aul t ) figure 25 - irda receive timing
194 t1 t1 t1 t1 t1 t1 t1 t2 t2 t2 t2 t2 t2 t2 parameter mi n 1.41 1.41 1.41 1.41 1.41 1.41 1.41 ma x 2.71 3.69 5.53 11.07 22.13 44.27 88.55 units s s s s s s s s s s s s s s pulse width at 115kbaud pulse width at 57.6kbaud pulse width at 38.4kbaud pulse width at 19.2kbaud pulse widt h at 9. 6kbaud pulse widt h at 4. 8kbaud pulse widt h at 2. 4kbaud bit t ime at 115kbaud bit time at 57. 6kbaud bit time at 38. 4kbaud bit time at 19. 2kbaud bit time at 9.6kbaud bit time at 4.8kbaud bit time at 2.4kbaud typ 1.6 3.22 4.8 9.7 19.5 39 78 8.68 17.4 26 52 104 208 416 t1 t2 t2 t1 0 10 1 0 0 11 0 11 dat a irtx n i rt x notes: 1. irda @ 115k i s hpsir compati ble. irda @ 2400 wi ll al low compat ibility with hp95lx and 48sx. 2. ir t x: l5 , c rf 1 b it 1 = 1 (de f ault) nirt x: l5, crf1 bit 1 = 0 figure 26 - irda transmit timing
195 t1 t2 t3 t4 t5 t6 pa rameter min typ max units 0.8 0.8 0.8 0.8 1.2 1.2 1.2 1.2 s s s s s s m odu lated out put b it t ime off bit t ime m odu l ated outp ut " on" m odu l ated out put " off" m odu l ated outp ut " on" m odu l ated out put " off" 1 1 1 1 note s: 1 . irrx: l 5, crf 1 bit 0 = 1 n irrx: l5 , crf 1 bit 0 = 0 (de fault) m irrx, nmi rrx are the mod ulate d ou t p uts t1 t2 t3 t4 t5 t6 01010011011 dat a irrx n irrx mirrx nm irrx figure 27 ? amplitude shift keyed ir receive timing
196 t1 t2 t3 t4 t5 t6 parameter min typ max units 0.8 0.8 0.8 0.8 1.2 1.2 1.2 1.2 s s s s s s m odu lated out put bit t ime off b it t ime m odu lated outp ut " on" m odu lated outp ut " off" m odu lated outp ut " on" m odu lated outp ut " off" 1 1 1 1 note s: 1 . irt x: l5 , crf 1 bit 1 = 1 (def ault) ni rtx: l 5, crf 1 bit 1 = 0 mirt x, nm irt x a re the mod ulate d ou tpu ts t1 t2 t3 t4 t5 t6 01010 011011 dat a irt x n irt x mir t x nmirtx figure 28 ? amplitude shift keyed ir transmit timing
197 t2 t1 pci_clk ser_irq figure 29 ? setup and hold time name description min typ max units t1 ser_irq setup time to pci_clk rising 7 nsec t2 ser_irq hold time to pci_clk rising 0 nsec data (5-8 bits) t1 data txd1, 2 start parity stop (1-2 bits) figure 30 ? serial port data name description min typ max units t1 serial port data bit time t br 1 nsec note 1: t br is 1/baud rate. the baud rate is programm ed through the divisor latch registers. baud rates have percentage errors indicated in the ?baud rate? table in the ?serial port? section.
198 package outlines figure 31 ? 100 pin tqfp and 100 pin tqn (lead-free) package outline mi n nominal max remark a ~ ~ 1.60 overall package height a1 0.05 ~ ~ standoff a2 1.35 1.40 1.45 body thickness d 15.80 16.00 16.20 x span d/2 7.90 8.00 8.10 1 / 2 x span measure from centerline d1 13.90 14.00 14.10 x body size e 15.80 16.00 16.20 y span e/2 7.90 8.00 8.10 1 / 2 y span measure from centerline e1 13.90 14.00 14.10 y body size h ~ ~ 0.20 lead frame thickness l 0.45 0.60 0.75 lead foot length from centerline l1 ~ 1.00 ~ lead length e 0.50 basic lead pitch ccc ~ ~ 0.0762 coplanarity (assemblers) ccc ~ ~ 0.08 coplanarity (test house)
199 notes: 1 controlling unit: millimeter 2 tolerance on the position of th e leads is 0.04 mm maximum. 3 package body dimensions d1 and e1 do not include the mold protrusion. maximum mold protrusion is 0.25 mm. 4 dimension for foot length l me asured at the gauge plane 0.25 mm above the seating plane is 0.78- 1.08 mm. 5 details of pin 1 identifier are optional but must be located within the zone indicated. 6 shoulder widths must conform to jedec ms -026 dimension 's' of a minimum of 0.20mm.
200 (ddd) figure 32 ? 100 pin stqfp and 100 pin stqn (lead-free) package outline mi n nominal max remark a ~ ~ 1.60 overall package height a1 0.05 ~ 0.15 standoff a2 1.35 1.40 1.45 body thickness d 13.80 14.00 14.20 x span d/2 6.90 7.00 7.10 1 / 2 x span measure from centerline d1 11.80 12.00 12.20 x body size e 13.80 14.00 14.20 y span e/2 6.90 7.00 7.10 1 / 2 y span measure from centerline e1 11.80 12.00 12.20 y body size h 0.09 ~ 0.20 lead frame thickness l 0.45 0.60 0.75 lead foot length from centerline l1 ~ 1.00 ~ lead length e 0.40 basic lead pitch t 0 o 3.5 o 7 o lead foot angle w 0.13 0.16 0.23 lead width r1 0.08 ~ ~ lead shoulder radius r2 0.08 ~ 0.20 lead foot radius ccc ~ ~ .0762 coplanarity (assemblers) ccc ~ ~ 0.08 coplanarity (test house) ddd ~ ~ 0.035 true position spread (bent leads)
201 notes: 1 controlling unit: millimeter 2 minimum space between protrusion and an adjacent lead is .007 mm. 3 details of pin 1 identifier ar e optional but must be located within the zone indicated. 4 dimension for foot length l measured at the gauge plane 0.25 mm abov e the seating plane. 5 shoulder widths must conform to jedec ms -026 dimension 's' of a minimum of 0.20mm.
202 80 arkay drive hauppauge, ny 11788 (631) 435-6000 fax (631) 273-3123 copyright ? smsc 2005. all rights reserved. circuit diagrams and other information rela ting to smsc products are included as a m eans of illustrating typical applications. consequently, complete information sufficient for construction purposes is not necessarily given. although the information has been checked and is believed to be accurate, no re sponsibility is assumed for inaccuracies. sm sc reserves the right to make changes to specifications and pr oduct descriptions at any time without notice. contact your local smsc sales office to obtain the latest specifications before placing your product order. the pr ovision of this informat ion does not convey to the purchaser of the des cribed semiconductor devices any lic enses under any patent rights or ot her intellectual property rights of smsc or others. all sales a re expressly conditional on your agreement to the terms and conditions of the most recently dated ve rsion of smsc's standard terms of sale agreement dated before the dat e of your order (the "terms of sale agreem ent"). the product may cont ain design defects or errors known as anomalies which may cause the product's f unctions to deviate from published s pecifications. a nomaly sheets are available upon request. smsc products are not designed, intended, aut horized or warranted for use in any life support or other application where product failure c ould cause or contribute to per sonal injury or severe property damage. any and all such uses without prior written approval of an office r of smsc and further testing and/or modifi cation will be fully at the risk of the c ustomer. copies of this document or ot her smsc literature, as well as the terms of sale agreement, may be obtained by visiting smsc?s website at http://www.smsc.com. smsc is a registered tr ademark of standard microsystems co rporation (?smsc?). product names and company names are the trademarks of their respective holders. smsc disclaims and excludes any and all warranties, including without limitation any and all implied warranties of merchantability, fitness for a particular purpose, title, and against infringement and the like, and any and all warranties arising from any course of dealing or usage of trade. in no event shall smsc be liable for any dire ct, incidental, indirect, special, punitive, or consequential damages; or for lost data, profit s, savings or revenues of any kind; regardless of the form of action, whether based on contract; tort; negligence of smsc or others; strict liability; breach of warranty; or otherwise; whet her or not any remedy of buyer is held to have failed of its essential purpose, and whether or not smsc has been advised of the possibility of such damages. lpc47n227 rev. 05/04/2005

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